// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
+
#ifndef _ROM_AES_H_
#define _ROM_AES_H_
void ets_aes_disable(void);
void ets_aes_set_endian(bool key_word_swap, bool key_byte_swap,
- bool in_word_swap, bool in_byte_swap,
- bool out_word_swap, bool out_byte_swap);
+ bool in_word_swap, bool in_byte_swap,
+ bool out_word_swap, bool out_byte_swap);
bool ets_aes_setkey_enc(const uint8_t *key, enum AES_BITS bits);
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
+
#ifndef _ROM_BIGINT_H_
#define _ROM_BIGINT_H_
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
+
#ifndef _ROM_CACHE_H_
#define _ROM_CACHE_H_
*
* @param int pod : process identifier. Range 0~7.
*
- * @param unsigned int vaddr : virtual address in CPU address space.
+ * @param unsigned int vaddr : virtual address in CPU address space.
* Can be IRam0, IRam1, IRom0 and DRom0 memory address.
* Should be aligned by psize.
*
*
* @param int pod : process identifier. Range 0~7.
*
- * @param unsigned int vaddr : virtual address in CPU address space.
+ * @param unsigned int vaddr : virtual address in CPU address space.
* Can be IRam0, IRam1, IRom0 and DRom0 memory address.
* Should be aligned by psize.
*
* 4 : mmu table to be written is out of range
* 5 : vaddr is out of range
*/
-
unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
/**
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
+
#ifndef ROM_CRC_H
#define ROM_CRC_H
+#include <stdint.h>
+
#ifdef __cplusplus
extern "C" {
#endif
/* Standard CRC8/16/32 algorithms. */
-// CRC-8 x8+x2+x1+1 0x07
+// CRC-8 x8+x2+x1+1 0x07
// CRC16-CCITT x16+x12+x5+1 1021 ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS
-// CRC32:
+// CRC32:
//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
//If your buf is not continuous, you can use the first result to be the second parameter.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
- * @param uint8_t const * buf : buffer to start calculate crc.
+ * @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
-uint32_t crc32_le(uint32_t crc, uint8_t const * buf, uint32_t len);
+uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc32 value that is in big endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
- * @param uint8_t const * buf : buffer to start calculate crc.
+ * @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
-uint32_t crc32_be(uint32_t crc, uint8_t const * buf, uint32_t len);
+uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc16 value that is in little endian.
*
* @param uint16_t crc : init crc value, use 0 at the first use.
*
- * @param uint8_t const * buf : buffer to start calculate crc.
+ * @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
-uint16_t crc16_le(uint16_t crc, uint8_t const * buf, uint32_t len);
+uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc16 value that is in big endian.
*
* @param uint16_t crc : init crc value, use 0 at the first use.
*
- * @param uint8_t const * buf : buffer to start calculate crc.
+ * @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
-uint16_t crc16_be(uint16_t crc, uint8_t const * buf, uint32_t len);
+uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc8 value that is in little endian.
*
* @param uint8_t crc : init crc value, use 0 at the first use.
*
- * @param uint8_t const * buf : buffer to start calculate crc.
+ * @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
-uint8_t crc8_le(uint8_t crc, uint8_t const * buf, uint32_t len);
+uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
/**
* @brief Crc8 value that is in big endian.
*
* @param uint32_t crc : init crc value, use 0 at the first use.
*
- * @param uint8_t const * buf : buffer to start calculate crc.
+ * @param uint8_t const *buf : buffer to start calculate crc.
*
* @param uint32_t len : buffer length in byte.
*
* @return None
*/
-uint8_t crc8_be(uint8_t crc, uint8_t const * buf, uint32_t len);
+uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
/**
* @}
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
+
#ifndef _ROM_EFUSE_H_
#define _ROM_EFUSE_H_
+#include <stdint.h>
+
#ifdef __cplusplus
extern "C" {
#endif
/** \defgroup efuse_APIs efuse APIs
* @brief ESP32 efuse read/write APIs
- * @attention
- *
+ * @attention
+ *
*/
/** @addtogroup efuse_APIs
*
* @return null
*/
-void ets_efuse_read_op(viid);
+void ets_efuse_read_op(void);
/**
* @brief Do a efuse write operation, to update efuse write registers to efuse, then you need call ets_efuse_read_op again.
*
* @return u32: 1 for 100KHZ.
*/
-u32 ets_efuse_get_8M_clock(void);
+uint32_t ets_efuse_get_8M_clock(void);
/**
* @brief Read spi pad configuration, show gpio number of flash pad, includes 5 pads.
*
* @param null
*
- * @return uint32_t: 0, invalid, flash pad decided by strapping
- * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
+ * @return uint32_t: 0, invalid, flash pad decided by strapping
+ * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*/
-
uint32_t ets_efuse_get_spiconfig(void);
/**
* @brief A crc8 algorithm used in efuse check.
*
- * @param unsigned char const * p : Pointer to original data.
+ * @param unsigned char const *p : Pointer to original data.
*
* @param unsigned int len : Data length in byte.
*
* @return unsigned char: Crc value.
*/
-unsigned char esp_crc8(unsigned char const * p, unsigned int len);
+unsigned char esp_crc8(unsigned char const *p, unsigned int len);
/**
* @}
*/
-
#ifdef __cplusplus
}
#endif
* NOTE
* Many functions in this header files can't be run in FreeRTOS.
* Please see the comment of the Functions.
- * There are also some functions that doesn't work on FreeRTOS
+ * There are also some functions that doesn't work on FreeRTOS
* without listed in the header, such as:
* xtos functions start with "_xtos_" in ld file.
- *
+ *
***********************************************************************
*/
* @{
*/
-
typedef enum {
- ETS_OK = 0,/**< return successful in ets*/
- ETS_FAILED = 1/**< return failed in ets*/
+ ETS_OK = 0, /**< return successful in ets*/
+ ETS_FAILED = 1 /**< return failed in ets*/
} ETS_STATUS;
typedef uint32_t ETSSignal;
typedef uint32_t ETSParam;
-typedef struct ETSEventTag ETSEvent;/**< Event transmit/receive in ets*/
+typedef struct ETSEventTag ETSEvent; /**< Event transmit/receive in ets*/
struct ETSEventTag {
- ETSSignal sig;/**< Event signal, in same task, different Event with different signal*/
- ETSParam par;/**< Event parameter, sometimes without usage, then will be set as 0*/
+ ETSSignal sig; /**< Event signal, in same task, different Event with different signal*/
+ ETSParam par; /**< Event parameter, sometimes without usage, then will be set as 0*/
};
-typedef void (*ETSTask)(ETSEvent *e);/**< Type of the Task processer*/
-typedef void (* ets_idle_cb_t)(void *arg);/**< Type of the system idle callback*/
+typedef void (*ETSTask)(ETSEvent *e); /**< Type of the Task processer*/
+typedef void (* ets_idle_cb_t)(void *arg); /**< Type of the system idle callback*/
/**
* @brief Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it.
* @return ETS_OK : post successful
* @return ETS_FAILED : post failed
*/
-ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
+ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
+
/**
* @}
*/
* @{
*/
-
-extern const char* const exc_cause_table[40];///**< excption cause that defined by the core.*/
+extern const char *const exc_cause_table[40]; ///**< excption cause that defined by the core.*/
/**
* @brief Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
*
* @param uint32_t pos : Flash physical address.
*
- * @param uint32_t* entry_addr: the pointer of an variable that can store Entry code address.
+ * @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
*
* @param bool jump : Jump into the code in the function or not.
*
*
* @param uint32_t pos : Flash physical address.
*
- * @param uint32_t* entry_addr: the pointer of an variable that can store Entry code address.
+ * @param uint32_t *entry_addr: the pointer of an variable that can store Entry code address.
*
* @param bool jump : Jump into the code in the function or not.
*
* @return ETS_FAILED : unpack failed
*/
ETS_STATUS ets_unpack_flash_code(uint32_t pos, uint32_t *entry_addr, bool jump, bool sb_need_check, bool config);
+
/**
* @}
*/
-
/** \defgroup ets_printf_apis, ets_printf related apis used in ets
* @brief ets printf apis
*/
* Can not print float point data format, or longlong data format.
* So we maybe only use this in ROM.
*
- * @param const char* fmt : See printf.
+ * @param const char *fmt : See printf.
*
* @param ... : See printf.
*
* @}
*/
-
/** \defgroup ets_timer_apis, ets_timer related apis used in ets
* @brief ets timer apis
*/
typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
typedef struct _ETSTIMER_ {
- struct _ETSTIMER_ *timer_next;/**< timer linker*/
- uint32_t timer_expire;/**< abstruct time when timer expire*/
- uint32_t timer_period;/**< timer period, 0 means timer is not periodic repeated*/
- ETSTimerFunc *timer_func;/**< timer handler*/
- void *timer_arg;/**< timer handler argument*/
+ struct _ETSTIMER_ *timer_next; /**< timer linker*/
+ uint32_t timer_expire; /**< abstruct time when timer expire*/
+ uint32_t timer_period; /**< timer period, 0 means timer is not periodic repeated*/
+ ETSTimerFunc *timer_func; /**< timer handler*/
+ void *timer_arg; /**< timer handler argument*/
} ETSTimer;
/**
*
* @return uint32_t : CPU ticks per us record in ets.
*/
-uint32_t ets_get_cpu_frequency();
+uint32_t ets_get_cpu_frequency(void);
/**
* @brief Get xtal_freq/analog_8M*256 value calibrated in rtc module.
*
* @return uint32_t : xtal_freq/analog_8M*256.
*/
-uint32_t ets_get_xtal_scale();
+uint32_t ets_get_xtal_scale(void);
/**
* @brief Get xtal_freq value, If value not stored in RTC_STORE5, than store.
*
* @param None
*
- * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
+ * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
* clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;
- * else if analog_8M in efuse
+ * else if analog_8M in efuse
* clock = ets_get_xtal_scale() * 15625 * ets_efuse_get_8M_clock() / 40;
* else clock = 26M.
*/
-uint32_t ets_get_detected_xtal_freq();
+uint32_t ets_get_detected_xtal_freq(void);
/**
* @}
*/
-
-
/** \defgroup ets_intr_apis, ets interrupt configure related apis
* @brief ets intr apis
*/
/**
* @brief Attach an CPU interrupt to a hardware source.
* We have 4 steps to use an interrupt:
- * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
+ * 1.Attach hardware interrupt source to CPU. intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
* 2.Set interrupt handler. xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
* 3.Enable interrupt for CPU. xt_ints_on(1 << ETS_WMAC_INUM);
* 4.Enable interrupt in the module.
#define ETS_TG0_T0_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_TG0_T0_INUM, (func), (void *)(arg))
-
+
#define ETS_GPIO_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_GPIO_INUM, (func), (void *)(arg))
#define ETS_WDT_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_WDT_INUM, (func), (void *)(arg))
-
+
#define ETS_SLC_INTR_ATTACH(func, arg) \
ETS_ISR_ATTACH(ETS_SLC_INUM, (func), (void *)(arg))
#define ETS_GPIO_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_GPIO_INUM)
-
+
#define ETS_WDT_INTR_ENABLE() \
ETS_INTR_ENABLE(ETS_WDT_INUM)
#define ETS_SLC_INTR_DISABLE() \
ETS_INTR_DISABLE(ETS_SLC_INUM)
-
#endif
+
/**
* @}
*/
-
#ifndef MAC2STR
#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
#endif
#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
+
/**
* @}
*/
* @{
*/
-
#define GPIO_REG_READ(reg) READ_PERI_REG(reg)
#define GPIO_REG_WRITE(reg, val) WRITE_PERI_REG(reg, val)
#define GPIO_PIN_COUNT 40
#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
-typedef enum{
- GPIO_PIN_INTR_DISABLE = 0,
- GPIO_PIN_INTR_POSEDGE = 1,
- GPIO_PIN_INTR_NEGEDGE = 2,
- GPIO_PIN_INTR_ANYEGDE = 3,
- GPIO_PIN_INTR_LOLEVEL = 4,
- GPIO_PIN_INTR_HILEVEL = 5
-}GPIO_INT_TYPE;
+typedef enum {
+ GPIO_PIN_INTR_DISABLE = 0,
+ GPIO_PIN_INTR_POSEDGE = 1,
+ GPIO_PIN_INTR_NEGEDGE = 2,
+ GPIO_PIN_INTR_ANYEGDE = 3,
+ GPIO_PIN_INTR_LOLEVEL = 4,
+ GPIO_PIN_INTR_HILEVEL = 5
+} GPIO_INT_TYPE;
#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
((gpio_no < 32) ? gpio_output_set(bit_value<<gpio_no, (bit_value ? 0 : 1)<<gpio_no, 1<<gpio_no,0) : \
/**
* @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
- * There is no particular ordering guaranteed; so if the order of writes is significant,
+ * There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
* @param uint32_t set_mask : the gpios that need high level.
/**
* @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
- * There is no particular ordering guaranteed; so if the order of writes is significant,
+ * There is no particular ordering guaranteed; so if the order of writes is significant,
* calling code should divide a single call into multiple calls.
*
* @param uint32_t set_mask : the gpios that need high level.
/**
* @brief Sample the value of GPIO input pins(0-31) and returns a bitmask.
- *
+ *
* @param None
- *
+ *
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
*/
uint32_t gpio_input_get(void);
/**
* @brief Sample the value of GPIO input pins(32-39) and returns a bitmask.
- *
+ *
* @param None
- *
+ *
* @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32.
*/
uint32_t gpio_input_get_high(void);
* @brief Register an application-specific interrupt handler for GPIO pin interrupts.
* Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack.
* Please do not call this function in SDK.
- *
+ *
* @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler
- *
+ *
* @param void *arg : gpio application-specific interrupt handler argument.
- *
+ *
* @return None
*/
void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg);
/**
* @brief Get gpio interrupts which happens but not processed.
* Please do not call this function in SDK.
- *
+ *
* @param None
- *
+ *
* @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0.
*/
uint32_t gpio_intr_pending(void);
/**
* @brief Get gpio interrupts which happens but not processed.
* Please do not call this function in SDK.
- *
+ *
* @param None
- *
+ *
* @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32.
*/
uint32_t gpio_intr_pending_high(void);
/**
* @brief Ack gpio interrupts to process pending interrupts.
* Please do not call this function in SDK.
- *
+ *
* @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0.
- *
+ *
* @return None
*/
void gpio_intr_ack(uint32_t ack_mask);
/**
* @brief Ack gpio interrupts to process pending interrupts.
* Please do not call this function in SDK.
- *
+ *
* @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32.
- *
+ *
* @return None
*/
void gpio_intr_ack_high(uint32_t ack_mask);
/**
* @brief Set GPIO to wakeup the ESP32.
* Please do not call this function in SDK.
- *
+ *
* @param uint32_t i: gpio number.
- *
+ *
* @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
- *
+ *
* @return None
*/
void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
/**
* @brief disable GPIOs to wakeup the ESP32.
* Please do not call this function in SDK.
- *
+ *
* @param None
- *
+ *
* @return None
*/
-void gpio_pin_wakeup_disable();
+void gpio_pin_wakeup_disable(void);
/**
* @brief set gpio input to a signal, one gpio can input to several signals.
- *
+ *
* @param uint32_t gpio : gpio number, 0~0x27
* gpio == 0x30, input 0 to signal
* gpio == 0x34, ???
* gpio == 0x38, input 1 to signal
*
* @param uint32_t signal_idx : signal index.
- *
- * @param bool inv : the signal is inv or not
- *
+ *
+ * @param bool inv : the signal is inv or not
+ *
* @return None
*/
void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
/**
* @brief set signal output to gpio, one signal can output to several gpios.
- *
+ *
* @param uint32_t gpio : gpio number, 0~0x27
*
* @param uint32_t signal_idx : signal index.
* signal_idx == 0x100, cancel output put to the gpio
- *
- * @param bool out_inv : the signal output is inv or not
- *
- * @param bool oen_inv : the signal output enable is inv or not
- *
+ *
+ * @param bool out_inv : the signal output is inv or not
+ *
+ * @param bool oen_inv : the signal output enable is inv or not
+ *
* @return None
*/
void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv);
/**
* @brief Select pad as a gpio function from IOMUX.
- *
+ *
* @param uint32_t gpio_num : gpio number, 0~0x27
- *
+ *
* @return None
*/
void gpio_pad_select_gpio(uint8_t gpio_num);
/**
* @brief Set pad driver capability.
- *
+ *
* @param uint32_t gpio_num : gpio number, 0~0x27
- *
+ *
* @param uint8_t drv : 0-3
- *
+ *
* @return None
*/
void gpio_pad_set_drv(uint8_t gpio_num, uint8_t drv);
/**
* @brief Pull up the pad from gpio number.
- *
+ *
* @param uint32_t gpio_num : gpio number, 0~0x27
- *
+ *
* @return None
*/
void gpio_pad_pullup(uint8_t gpio_num);
/**
* @brief Pull down the pad from gpio number.
- *
+ *
* @param uint32_t gpio_num : gpio number, 0~0x27
- *
+ *
* @return None
*/
void gpio_pad_pulldown(uint8_t gpio_num);
/**
* @brief Unhold the pad from gpio number.
- *
+ *
* @param uint32_t gpio_num : gpio number, 0~0x27
- *
+ *
* @return None
*/
void gpio_pad_unhold(uint8_t gpio_num);
/**
* @brief Hold the pad from gpio number.
- *
+ *
* @param uint32_t gpio_num : gpio number, 0~0x27
- *
+ *
* @return None
*/
void gpio_pad_hold(uint8_t gpio_num);
* Please do not use reserved or used rtc memory or registers. *
* *
*************************************************************************************
- * RTC Memory & Store Register usage
+ * RTC Memory & Store Register usage
*************************************************************************************
* rtc memory addr type size usage
* 0x3ff61000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
- * 0x3ff61000+SIZE_CP Slow 7936-SIZE_CP
- * 0x3ff62f00 Slow 256 Reserved
+ * 0x3ff61000+SIZE_CP Slow 6144-SIZE_CP
+ * 0x3ff62800 Slow 2048 Reserved
*
* 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code
*
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
EXT_CPU_RESET = 14, /**<14, for APP CPU, reseted by PRO CPU*/
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
- RTCWDT_RTC_RESET = 16 /**<16, RTC Watch dog reset digital core and rtc module*/
+ RTCWDT_RTC_RESET = 16 /**<16, RTC Watch dog reset digital core and rtc module*/
} RESET_REASON;
typedef enum {
SDIO_IDLE_INT_EN = SDIO_IDLE_INT,
RTC_WDT_INT_EN = RTC_WDT_INT,
RTC_TIME_VALID_INT_EN = RTC_TIME_VALID_INT
-}RTC_INT_EN;
+} RTC_INT_EN;
/**
* @brief Get the reset reason for CPU.
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
+
#ifndef _ROM_SECURE_BOOT_H_
#define _ROM_SECURE_BOOT_H_
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
+
#ifndef _ROM_SPI_FLASH_H_
#define _ROM_SPI_FLASH_H_
/*************************************************************
* Note
*************************************************************
- * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
- * used as an SPI master to access Flash and ext-SRAM by
- * Cache module. It will support Decryto read for Flash,
- * read/write for ext-SRAM. And SPI1 is also used as an
- * SPI master for Flash read/write and ext-SRAM read/write.
+ * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is
+ * used as an SPI master to access Flash and ext-SRAM by
+ * Cache module. It will support Decryto read for Flash,
+ * read/write for ext-SRAM. And SPI1 is also used as an
+ * SPI master for Flash read/write and ext-SRAM read/write.
* It will support Encrypto write for Flash.
* 2. As an SPI master, SPI support Highest clock to 80M,
- * however, Flash with 80M Clock should be configured
- * for different Flash chips. If you want to use 80M
- * clock We should use the SPI that is certified by
- * Espressif. However, the certification is not started
+ * however, Flash with 80M Clock should be configured
+ * for different Flash chips. If you want to use 80M
+ * clock We should use the SPI that is certified by
+ * Espressif. However, the certification is not started
* at the time, so please use 40M clock at the moment.
- * 3. SPI Flash can use 2 lines or 4 lines mode. If you
- * use 2 lines mode, you can save two pad SPIHD and
- * SPIWP for gpio. ESP32 support configured SPI pad for
- * Flash, the configuration is stored in efuse and flash.
+ * 3. SPI Flash can use 2 lines or 4 lines mode. If you
+ * use 2 lines mode, you can save two pad SPIHD and
+ * SPIWP for gpio. ESP32 support configured SPI pad for
+ * Flash, the configuration is stored in efuse and flash.
* However, the configurations of pads should be certified
- * by Espressif. If you use this function, please use 40M
+ * by Espressif. If you use this function, please use 40M
* clock at the moment.
- * 4. ESP32 support to use Common SPI command to configure
+ * 4. ESP32 support to use Common SPI command to configure
* Flash to QIO mode, if you failed to configure with fix
* command. With Common SPI Command, ESP32 can also provide
* a way to use same Common SPI command groups on different
* Flash chips.
- * 5. This functions are not protected by packeting, Please use the
+ * 5. This functions are not protected by packeting, Please use the
*************************************************************
*/
SPI_FLASH_RESULT_TIMEOUT
} SpiFlashOpResult;
-typedef struct{
+typedef struct {
uint32_t deviceId;
uint32_t chip_size; // chip size in bytes
uint32_t block_size;
/**
* @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
- * Please do not call this function in SDK.
+ * Please do not call this function in SDK.
*
* @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
*
/**
* @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
- * Please do not call this function in SDK.
+ * Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
- * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+ * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
/**
* @brief Set SPI Flash pad drivers.
- * Please do not call this function in SDK.
+ * Please do not call this function in SDK.
*
* @param uint8_t wp_gpio_num: WP gpio number.
*
- * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+ * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
- * @param uint8_t* drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
- * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
+ * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
+ * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
* Values usually read from falsh by rom code, function usually callde by rom code.
* if value with bit(3) set, the value is valid, bit[2:0] is the real value.
*
* @return None
*/
-void SetSpiDrvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t* drvs);
+void SetSpiDrvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
/**
* @brief Select SPI Flash function for pads.
- * Please do not call this function in SDK.
+ * Please do not call this function in SDK.
*
- * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+ * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @return None
/**
* @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
- * Please do not call this function in SDK.
+ * Please do not call this function in SDK.
*
- * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+ * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
* else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
*
* @param uint8_t legacy: In legacy mode, more SPI command is used in line.
*/
void spi_flash_attach(uint32_t ishspi, bool legacy);
-
-//void spi_cache_sram_init();
-
/**
* @brief SPI Read Flash status register. We use CMD 0x05.
- * Please do not call this function in SDK.
+ * Please do not call this function in SDK.
*
- * @param SpiFlashChip * spi : The information for Flash, which is exported from ld file.
+ * @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
*
- * @param uint32_t* status : The pointer to which to return the Flash status value.
+ * @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return SPI_FLASH_RESULT_OK : read OK.
* SPI_FLASH_RESULT_ERR : read error.
* SPI_FLASH_RESULT_TIMEOUT : read timeout.
*/
-SpiFlashOpResult SPI_read_status(SpiFlashChip * spi, uint32_t * status);
+SpiFlashOpResult SPI_read_status(SpiFlashChip *spi, uint32_t *status);
/**
* @brief SPI Read Flash status register high 16 bit. We use CMD 0x35.
* Please do not call this function in SDK.
*
- * @param SpiFlashChip * spi : The information for Flash, which is exported from ld file.
+ * @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
*
- * @param uint32_t* status : The pointer to which to return the Flash status value.
+ * @param uint32_t *status : The pointer to which to return the Flash status value.
*
* @return SPI_FLASH_RESULT_OK : read OK.
* SPI_FLASH_RESULT_ERR : read error.
* SPI_FLASH_RESULT_TIMEOUT : read timeout.
*/
-SpiFlashOpResult SPI_read_status_high(SpiFlashChip * spi, uint32_t * status);
+SpiFlashOpResult SPI_read_status_high(SpiFlashChip *spi, uint32_t *status);
/**
* @brief Write status to Falsh status register.
* Please do not call this function in SDK.
*
- * @param SpiFlashChip * spi : The information for Flash, which is exported from ld file.
+ * @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
*
- * @param uint32_t status_value : Value to .
+ * @param uint32_t status_value : Value to .
*
* @return SPI_FLASH_RESULT_OK : write OK.
* SPI_FLASH_RESULT_ERR : write error.
* SPI_FLASH_RESULT_TIMEOUT : write timeout.
*/
-SpiFlashOpResult SPI_write_status(SpiFlashChip * spi, uint32_t status_value);
+SpiFlashOpResult SPI_write_status(SpiFlashChip *spi, uint32_t status_value);
/**
- * @brief Use a command to Read Flash status register.
+ * @brief Use a command to Read Flash status register.
* Please do not call this function in SDK.
*
- * @param SpiFlashChip * spi : The information for Flash, which is exported from ld file.
+ * @param SpiFlashChip *spi : The information for Flash, which is exported from ld file.
*
- * @param uint32_t* status : The pointer to which to return the Flash status value.
+ * @param uint32_t*status : The pointer to which to return the Flash status value.
*
* @return SPI_FLASH_RESULT_OK : read OK.
* SPI_FLASH_RESULT_ERR : read error.
* SPI_FLASH_RESULT_TIMEOUT : read timeout.
*/
-SpiFlashOpResult SPI_user_command_read(uint32_t * status, uint8_t cmd);
+SpiFlashOpResult SPI_user_command_read(uint32_t *status, uint8_t cmd);
/**
* @brief Config SPI Flash read mode when init.
* @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
* Please do not call this function in SDK.
*
- * @param SpiCommonCmd * cmd : A struct to show the action of a command.
+ * @param SpiCommonCmd *cmd : A struct to show the action of a command.
*
* @return uint16_t 0 : do not send command any more.
* 1 : go to the next command.
- * n > 1 : skip (n - 1) commands.
+ * n > 1 : skip (n - 1) commands.
*/
-uint16_t SPI_Common_Command(SpiCommonCmd * cmd);
+uint16_t SPI_Common_Command(SpiCommonCmd *cmd);
/**
* @brief Unlock SPI write protect.
* SPI_FLASH_RESULT_ERR : Unlock error.
* SPI_FLASH_RESULT_TIMEOUT : Unlock timeout.
*/
-SpiFlashOpResult SPIUnlock();
+SpiFlashOpResult SPIUnlock(void);
/**
* @brief SPI write protect.
* SPI_FLASH_RESULT_ERR : Lock error.
* SPI_FLASH_RESULT_TIMEOUT : Lock timeout.
*/
-SpiFlashOpResult SPILock();
+SpiFlashOpResult SPILock(void);
/**
* @brief Update SPI Flash parameter.
/**
* @brief Write Data to Flash, you should Erase it yourself if need.
- * Please do not call this function in SDK.
+ * Please do not call this function in SDK.
*
* @param uint32_t dest_addr : Address to write, should be 4 bytes aligned.
*
- * @param const uint32_t* src : The pointer to data which is to write.
+ * @param const uint32_t *src : The pointer to data which is to write.
*
* @param uint32_t len : Length to write, should be 4 bytes aligned.
*
* SPI_FLASH_RESULT_ERR : Write error.
* SPI_FLASH_RESULT_TIMEOUT : Write timeout.
*/
-SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t* src, int32_t len);
+SpiFlashOpResult SPIWrite(uint32_t dest_addr, const uint32_t *src, int32_t len);
/**
* @brief Read Data from Flash, you should Erase it yourself if need.
- * Please do not call this function in SDK.
+ * Please do not call this function in SDK.
*
* @param uint32_t src_addr : Address to read, should be 4 bytes aligned.
*
- * @param uint32_t* data : The buf to read the data.
+ * @param uint32_t *dest : The buf to read the data.
*
* @param uint32_t len : Length to read, should be 4 bytes aligned.
*
* SPI_FLASH_RESULT_ERR : Read error.
* SPI_FLASH_RESULT_TIMEOUT : Read timeout.
*/
-SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t* dest, int32_t len);
+SpiFlashOpResult SPIRead(uint32_t src_addr, uint32_t *dest, int32_t len);
/**
* @brief SPI1 go into encrypto mode.
- * Please do not call this function in SDK.
+ * Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
-void SPI_Write_Encrypt_Enable();
+void SPI_Write_Encrypt_Enable(void);
/**
* @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need.
- * Please do not call this function in SDK.
+ * Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 bytes aligned.
*
- * @param uint32_t* data : The pointer to data which is to write.
+ * @param uint32_t *data : The pointer to data which is to write.
*
* @return SPI_FLASH_RESULT_OK : Prepare OK.
* SPI_FLASH_RESULT_ERR : Prepare error.
* SPI_FLASH_RESULT_TIMEOUT : Prepare timeout.
*/
-SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t* data);
+SpiFlashOpResult SPI_Prepare_Encrypt_Data(uint32_t flash_addr, uint32_t *data);
/**
* @brief SPI1 go out of encrypto mode.
- * Please do not call this function in SDK.
+ * Please do not call this function in SDK.
*
* @param None
*
* @return None
*/
-void SPI_Write_Encrypt_Disable();
+void SPI_Write_Encrypt_Disable(void);
/**
* @brief Encrpto writing data to flash, you should Erase it yourself if need.
- * Please do not call this function in SDK.
+ * Please do not call this function in SDK.
*
* @param uint32_t flash_addr : Address to write, should be 32 bytes aligned.
*
- * @param uint32_t* data : The pointer to data which is to write.
+ * @param uint32_t *data : The pointer to data which is to write.
*
* @param uint32_t len : Length to write, should be 32 bytes aligned.
*
* SPI_FLASH_RESULT_ERR : Encrypto write error.
* SPI_FLASH_RESULT_TIMEOUT : Encrypto write timeout.
*/
-SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, uint32_t* data, uint32_t len);
+SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, uint32_t *data, uint32_t len);
/**
* @}
#define UART_RCV_ERR_FLAG BIT7
//send and receive message frame head
-#define FRAME_FLAG 0x7E
+#define FRAME_FLAG 0x7E
-typedef enum{
+typedef enum {
UART_LINE_STATUS_INT_FLAG = 0x06,
UART_RCV_FIFO_INT_FLAG = 0x04,
UART_RCV_TMOUT_INT_FLAG = 0x0C,
} UartStopBitsNum;
typedef enum {
- NONE_BITS = 0,
- ODD_BITS = 2,
- EVEN_BITS = 3
+ NONE_BITS = 0,
+ ODD_BITS = 2,
+ EVEN_BITS = 3
} UartParityMode;
typedef enum {
EMPTY,
UNDER_WRITE,
- WRITE_OVER
+ WRITE_OVER
} RcvMsgBuffState;
typedef struct {
uint8_t *pRcvMsgBuff;
uint8_t *pWritePos;
uint8_t *pReadPos;
- uint8_t TrigLvl; //JLU: may need to pad
+ uint8_t TrigLvl;
RcvMsgBuffState BuffState;
-}RcvMsgBuff;
+} RcvMsgBuff;
typedef struct {
uint32_t TrxBuffSize;
RCV_ESC_CHAR,
} RcvMsgState;
-typedef struct{
+typedef struct {
UartBautRate baut_rate;
UartBitsNum4Char data_bits;
UartExistParity exist_parity;
*
* @return None
*/
-void uartAttach();
+void uartAttach(void);
/**
* @brief Init uart0 or uart1 for UART download booting mode.
* @brief Get an input char from message channel.
* Please do not call this function in SDK.
*
- * @param uint8_t* pRxChar : the pointer to store the char.
+ * @param uint8_t *pRxChar : the pointer to store the char.
*
* @return OK for successful.
* FAIL for failed.
*/
-STATUS uart_rx_one_char(uint8_t* pRxChar);
+STATUS uart_rx_one_char(uint8_t *pRxChar);
/**
* @brief Get an input char to message channel, wait until successful.
* @brief Get an input string line from message channel.
* Please do not call this function in SDK.
*
- * @param uint8_t* pString : the pointer to store the string.
+ * @param uint8_t *pString : the pointer to store the string.
*
* @param uint8_t MaxStrlen : the max string length, incude '\0'.
*
* @return OK.
*/
-STATUS UartRxString(uint8_t* pString, uint8_t MaxStrlen);
+STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
/**
* @brief Process uart recevied information in the interrupt handler.
* Please do not call this function in SDK.
*
- * @param void * para : the message receive buffer.
+ * @param void *para : the message receive buffer.
*
* @return None
*/
-void uart_rx_intr_handler(void * para);
+void uart_rx_intr_handler(void *para);
/**
* @brief Get an char from receive buffer.
* Please do not call this function in SDK.
*
- * @param RcvMsgBuff* pRxBuff : the pointer to the struct that include receive buffer.
+ * @param RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
*
- * @param uint8_t* pRxByte : the pointer to store the char.
+ * @param uint8_t *pRxByte : the pointer to store the char.
*
* @return OK for successful.
* FAIL for failed.
*/
-STATUS uart_rx_readbuff( RcvMsgBuff* pRxBuff, uint8_t* pRxByte);
+STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
/**
* @brief Get all chars from receive buffer.
* Please do not call this function in SDK.
*
- * @param uint8_t * pCmdLn : the pointer to store the string.
+ * @param uint8_t *pCmdLn : the pointer to store the string.
*
* @return OK for successful.
* FAIL for failed.
*/
-STATUS UartGetCmdLn(uint8_t * pCmdLn);
+STATUS UartGetCmdLn(uint8_t *pCmdLn);
/**
* @brief Get uart configuration struct.
*
* @return UartDevice * : uart configuration struct pointer.
*/
-UartDevice * GetUartDevice();
+UartDevice *GetUartDevice(void);
/**
- * @brief Send an packet to download tool, with ESC char.
+ * @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
- * @param uint8_t * p : the pointer to output string.
+ * @param uint8_t *p : the pointer to output string.
*
* @param int len : the string length.
*
void send_packet(uint8_t *p, int len);
/**
- * @brief Receive an packet from download tool, with ESC char.
+ * @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
- * @param uint8_t * p : the pointer to input string.
+ * @param uint8_t *p : the pointer to input string.
*
* @param int len : If string length > len, the string will be truncated.
*
*/
int recv_packet(uint8_t *p, int len, uint8_t is_sync);
-
/**
- * @brief Send an packet to download tool, with ESC char.
+ * @brief Send an packet to download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
- * @param uint8_t * pData : the pointer to input string.
+ * @param uint8_t *pData : the pointer to input string.
*
* @param uint16_t DataLen : the string length.
*
*/
STATUS SendMsg(uint8_t *pData, uint16_t DataLen);
-
/**
- * @brief Receive an packet from download tool, with ESC char.
+ * @brief Receive an packet from download tool, with SLIP escaping.
* Please do not call this function in SDK.
*
- * @param uint8_t * pData : the pointer to input string.
+ * @param uint8_t *pData : the pointer to input string.
*
* @param uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated.
*
#define PERIPHS_IO_MUX_MTDI_U (DR_REG_IO_MUX_BASE +0x34)
#define FUNC_MTDI_EMAC_TXD3 5
#define FUNC_MTDI_SD_DATA2 4
-#define FUNC_MTDI_HS2_DATA2 3
+#define FUNC_MTDI_HS2_DATA2 3
#define FUNC_MTDI_GPIO12 2
#define FUNC_MTDI_HSPIQ 1
#define FUNC_MTDI_MTDI 0
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