[X86] Improve use of SHLD/SHRD

Summary:
This extends the variety of pattern that can generate a SHLD instead of using two shifts.

This fixes a regression that would be introduced by D57367 or D33587

Reviewers: RKSimon, craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D57389

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355260 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index de666798b034fe6faadcdb5d5e0bc5ab66245056..fe2fd090e210de478f482ca00c821231722ab97b 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -37425,6 +37425,12 @@ static SDValue combineOr(SDNode *N, SelectionDAG &DAG,
     SDValue Sum = ShAmt1.getOperand(0);
     if (auto *SumC = dyn_cast<ConstantSDNode>(Sum)) {
       SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
+      if (ShAmt1Op1.getOpcode() == ISD::AND &&
+          isa<ConstantSDNode>(ShAmt1Op1.getOperand(1)) &&
+          ShAmt1Op1.getConstantOperandVal(1) == (Bits - 1)) {
+        ShMsk1 = ShAmt1Op1;
+        ShAmt1Op1 = ShAmt1Op1.getOperand(0);
+      }
       if (ShAmt1Op1.getOpcode() == ISD::TRUNCATE)
         ShAmt1Op1 = ShAmt1Op1.getOperand(0);
       if ((SumC->getAPIntValue() == Bits ||

diff --git a/test/CodeGen/X86/shift-double-x86_64.ll b/test/CodeGen/X86/shift-double-x86_64.ll
index 22993cd09dfa4e4347483a49b2b0de0961b95a72..a410595e03cf99b9c595bf91165139ebfaa709c3 100644 (file)
--- a/test/CodeGen/X86/shift-double-x86_64.ll
+++ b/test/CodeGen/X86/shift-double-x86_64.ll
@@ -118,14 +118,10 @@ define i64 @test7(i64 %hi, i64 %lo, i64 %bits) nounwind {
 define i64 @test8(i64 %hi, i64 %lo, i64 %bits) nounwind {
 ; CHECK-LABEL: test8:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rdx, %rcx
 ; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    movl %edx, %ecx
-; CHECK-NEXT:    andb $63, %cl
-; CHECK-NEXT:    negb %cl
-; CHECK-NEXT:    shrq %cl, %rsi
-; CHECK-NEXT:    movl %edx, %ecx
-; CHECK-NEXT:    shlq %cl, %rax
-; CHECK-NEXT:    orq %rsi, %rax
+; CHECK-NEXT:    # kill: def $cl killed $cl killed $rcx
+; CHECK-NEXT:    shldq %cl, %rsi, %rax
 ; CHECK-NEXT:    retq
   %tbits = trunc i64 %bits to i8
   %tand = and i8 %tbits, 63

diff --git a/test/CodeGen/X86/shift-double.ll b/test/CodeGen/X86/shift-double.ll
index 70d323957d264a76c28d7506fc3baef157998e5e..9621c9445937c143c5af16fba06002d40621b200 100644 (file)
--- a/test/CodeGen/X86/shift-double.ll
+++ b/test/CodeGen/X86/shift-double.ll
@@ -462,30 +462,18 @@ define i32 @test17(i32 %hi, i32 %lo, i32 %bits) nounwind {
 define i32 @test18(i32 %hi, i32 %lo, i32 %bits) nounwind {
 ; X86-LABEL: test18:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %esi
+; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %esi
-; X86-NEXT:    movb {{[0-9]+}}(%esp), %dl
-; X86-NEXT:    movl %edx, %ecx
-; X86-NEXT:    andb $31, %cl
-; X86-NEXT:    negb %cl
-; X86-NEXT:    shrl %cl, %esi
-; X86-NEXT:    movl %edx, %ecx
-; X86-NEXT:    shll %cl, %eax
-; X86-NEXT:    orl %esi, %eax
-; X86-NEXT:    popl %esi
+; X86-NEXT:    shldl %cl, %edx, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test18:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    movl %edx, %ecx
-; X64-NEXT:    andb $31, %cl
-; X64-NEXT:    negb %cl
-; X64-NEXT:    shrl %cl, %esi
 ; X64-NEXT:    movl %edx, %ecx
-; X64-NEXT:    shll %cl, %eax
-; X64-NEXT:    orl %esi, %eax
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
+; X64-NEXT:    shldl %cl, %esi, %eax
 ; X64-NEXT:    retq
   %tbits = trunc i32 %bits to i8
   %tand = and i8 %tbits, 31