Merge 81403 from mainline.

Fix double load / store multiple encoding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_26@81641 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 6218fceac1c215634d2cc684638a5a32fdb0ef44..4713b926e9318a2810941187cc4de8c771e4d77f 100644 (file)
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -963,7 +963,7 @@ static unsigned getAddrModeUPBits(unsigned Mode) {
   // DB - Decrement before - bit U = 0 and bit P = 1
   switch (Mode) {
   default: llvm_unreachable("Unknown addressing sub-mode!");
-  case ARM_AM::da:                      break;
+  case ARM_AM::da:                                     break;
   case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
   case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
   case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index deff83b1c9910108e3262e489076bb8a9035930b..355ba743bb5d4201cbb84ad244ae4a6f43c7b624 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -1070,7 +1070,7 @@ class ASI5<bits<4> opcod1, bits<2> opcod2, dag oops, dag iops,
 }
 
 // Load / store multiple
-class AXSI5<dag oops, dag iops, InstrItinClass itin,
+class AXDI5<dag oops, dag iops, InstrItinClass itin,
             string asm, list<dag> pattern>
   : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
        VFPLdStMulFrm, itin, asm, "", pattern> {
@@ -1079,7 +1079,7 @@ class AXSI5<dag oops, dag iops, InstrItinClass itin,
   let Inst{11-8}  = 0b1011;
 }
 
-class AXDI5<dag oops, dag iops, InstrItinClass itin,
+class AXSI5<dag oops, dag iops, InstrItinClass itin,
             string asm, list<dag> pattern>
   : VFPXI<oops, iops, AddrMode5, Size4Bytes, IndexModeNone,
        VFPLdStMulFrm, itin, asm, "", pattern> {
@@ -1088,7 +1088,6 @@ class AXDI5<dag oops, dag iops, InstrItinClass itin,
   let Inst{11-8}  = 0b1010;
 }
 
-
 // Double precision, unary
 class ADuI<bits<8> opcod1, bits<4> opcod2, bits<4> opcod3, dag oops, dag iops,
            InstrItinClass itin, string opc, string asm, list<dag> pattern>