[PowerPC][NFC] Make `getDefMIPostRA` public

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366995 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h
index 55047ade1c9d4ad664eff833f91f24ada50c35e7..5150650439bc62cc747a5e88efd5a7b4fe8a480e 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/lib/Target/PowerPC/PPCInstrInfo.h
@@ -140,11 +140,6 @@ class PPCInstrInfo : public PPCGenInstrInfo {
                                    unsigned &OpNoForForwarding,
                                    bool &SeenIntermediateUse) const;
 
-  // In PostRA phase, try to find instruction defines \p Reg before \p MI.
-  // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
-  MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI,
-                               bool &SeenIntermediateUse) const;
-
   // Can the user MI have it's source at index \p OpNoForForwarding
   // forwarded from an add-immediate that feeds it?
   bool isUseMIElgibleForForwarding(MachineInstr &MI, const ImmInstrInfo &III,
@@ -447,6 +442,11 @@ public:
   bool instrHasImmForm(unsigned Opc, bool IsVFReg, ImmInstrInfo &III,
                        bool PostRA) const;
 
+  // In PostRA phase, try to find instruction defines \p Reg before \p MI.
+  // \p SeenIntermediate is set to true if uses between DefMI and \p MI exist.
+  MachineInstr *getDefMIPostRA(unsigned Reg, MachineInstr &MI,
+                               bool &SeenIntermediateUse) const;
+
   /// getRegNumForOperand - some operands use different numbering schemes
   /// for the same registers. For example, a VSX instruction may have any of
   /// vs0-vs63 allocated whereas an Altivec instruction could only have