[InstCombine] Add test cases for missing support for turning vector sdiv into udiv...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300434 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/Transforms/InstCombine/div-shift.ll b/test/Transforms/InstCombine/div-shift.ll
index 517313ed8e4eda29b7db8de7c487abafd73a9a48..5642241c96feeb6a31fb36fb421135cc3bdc3d44 100644 (file)
--- a/test/Transforms/InstCombine/div-shift.ll
+++ b/test/Transforms/InstCombine/div-shift.ll
@@ -16,6 +16,21 @@ entry:
   ret i32 %d
 }
 
+define <2 x i32> @t1vec(<2 x i16> %x, <2 x i32> %y) {
+; CHECK-LABEL: @t1vec(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[CONV:%.*]] = zext <2 x i16> [[X:%.*]] to <2 x i32>
+; CHECK-NEXT:    [[S:%.*]] = shl nuw <2 x i32> <i32 2, i32 2>, [[Y:%.*]]
+; CHECK-NEXT:    [[D:%.*]] = sdiv <2 x i32> [[CONV]], [[S]]
+; CHECK-NEXT:    ret <2 x i32> [[D]]
+;
+entry:
+  %conv = zext <2 x i16> %x to <2 x i32>
+  %s = shl <2 x i32> <i32 2, i32 2>, %y
+  %d = sdiv <2 x i32> %conv, %s
+  ret <2 x i32> %d
+}
+
 ; rdar://11721329
 define i64 @t2(i64 %x, i32 %y) {
 ; CHECK-LABEL: @t2(

diff --git a/test/Transforms/InstCombine/div.ll b/test/Transforms/InstCombine/div.ll
index a037607267ac857d2c43c56e8996223161889938..99cd6962e9560a359e74dc775c8f053ebdc1c846 100644 (file)
--- a/test/Transforms/InstCombine/div.ll
+++ b/test/Transforms/InstCombine/div.ll
@@ -388,6 +388,17 @@ define i32 @test35(i32 %A) {
   ret i32 %mul
 }
 
+define <2 x i32> @test35vec(<2 x i32> %A) {
+; CHECK-LABEL: @test35vec(
+; CHECK-NEXT:    [[AND:%.*]] = and <2 x i32> [[A:%.*]], <i32 2147483647, i32 2147483647>
+; CHECK-NEXT:    [[MUL:%.*]] = sdiv exact <2 x i32> [[AND]], <i32 2147483647, i32 2147483647>
+; CHECK-NEXT:    ret <2 x i32> [[MUL]]
+;
+  %and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
+  %mul = sdiv exact <2 x i32> %and, <i32 2147483647, i32 2147483647>
+  ret <2 x i32> %mul
+}
+
 define i32 @test36(i32 %A) {
 ; CHECK-LABEL: @test36(
 ; CHECK-NEXT:    [[AND:%.*]] = and i32 %A, 2147483647