ARM: teach Sema that "r" can match 64-bit values

We already support using "r" on 64-bit values (a GPRPair is
allocated), but Sema doesn't know this yet so issues a warning. This
should fix it.

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@196724 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Basic/Targets.cpp b/lib/Basic/Targets.cpp
index 8950fa0ab7805a1da7e7b63980e0e15854f81349..e10bd9715445c39e4a08aa1809165c808a3c6c51 100644 (file)
--- a/lib/Basic/Targets.cpp
+++ b/lib/Basic/Targets.cpp
@@ -4110,7 +4110,7 @@ public:
     case 'r': {
       switch (Modifier) {
       default:
-        return (isInOut || isOutput || Size <= 32);
+        return (isInOut || isOutput || Size <= 64);
       case 'q':
         // A register of size 32 cannot fit a vector type.
         return false;

diff --git a/test/Sema/arm-asm.c b/test/Sema/arm-asm.c
index 3fc0eeb7543ab7275ba9a1b0d2ac69023426a747..e48718b0a2acaf02fb60d320f66a0bfee1654eb7 100644 (file)
--- a/test/Sema/arm-asm.c
+++ b/test/Sema/arm-asm.c
@@ -5,3 +5,8 @@ void f (void) {
   asm volatile ("lw (r1), %0[val]": "=&b"(Val)); // expected-error {{invalid output constraint '=&b' in asm}}
   return;
 }
+
+void test_64bit_r(void) {
+  long long foo = 0, bar = 0;
+  asm volatile("INST %0, %1" : "=r"(foo) : "r"(bar));
+}