[mips] Fix previous revert r281726.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281729 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index e9ec4c7d6472ebc4fdedef65b87e38700cd848ed..74a8f4f2152a19414e7550bd830a7e19e8c5f22e 100644 (file)
--- a/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -446,14 +446,6 @@ template <typename InsnType>
 static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
                                    const void *Decoder);
 
-template <typename InsnType>
-static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
-                                   const void *Decoder);
-
-template <typename InsnType>
-static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
-                                   const void *Decoder);
-
 template <typename InsnType>
 static DecodeStatus
 DecodeAddiGroupBranch(MCInst &MI, InsnType insn, uint64_t Address,
@@ -639,34 +631,6 @@ static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
   return MCDisassembler::Success;
 }
 
-template <typename InsnType>
-static DecodeStatus DecodeDAHIDATIMMR6(MCInst &MI, InsnType insn, uint64_t Address,
-                               const void *Decoder) {
-  InsnType Rt = fieldFromInstruction(insn, 16, 5);
-  InsnType Imm = fieldFromInstruction(insn, 0, 16);
-  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
-                                       Rt)));
-  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
-                                       Rt)));
-  MI.addOperand(MCOperand::createImm(Imm));
-
-  return MCDisassembler::Success;
-}
-
-template <typename InsnType>
-static DecodeStatus DecodeDAHIDATI(MCInst &MI, InsnType insn, uint64_t Address,
-                               const void *Decoder) {
-  InsnType Rt = fieldFromInstruction(insn, 21, 5);
-  InsnType Imm = fieldFromInstruction(insn, 0, 16);
-  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
-                                       Rt)));
-  MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID,
-                                       Rt)));
-  MI.addOperand(MCOperand::createImm(Imm));
-
-  return MCDisassembler::Success;
-}
-
 template <typename InsnType>
 static DecodeStatus DecodeAddiGroupBranch(MCInst &MI, InsnType insn,
                                           uint64_t Address,