]> granicus.if.org Git - llvm/commit
Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast...
authorCraig Topper <craig.topper@intel.com>
Mon, 13 May 2019 04:03:35 +0000 (04:03 +0000)
committerCraig Topper <craig.topper@intel.com>
Mon, 13 May 2019 04:03:35 +0000 (04:03 +0000)
commitfed0c65b298656841e10d061b86f0148ce6449c0
treefb1eadc086ca9a0c504fb5f33a5458c05093206c
parentce95266bfbadf5026c757ad79a90a42726dcf491
Recommit r358887 "[TargetLowering][AMDGPU][X86] Improve SimplifyDemandedBits bitcast handling"

I've included a new fix in X86RegisterInfo to prevent PR41619 without
reintroducing r359392. We might be able to improve that in the base class
implementation of shouldRewriteCopySrc somehow. But this hopefully enables
forward progress on SimplifyDemandedBits improvements for now.

Original commit message:

This patch adds support for BigBitWidth -> SmallBitWidth bitcasts, splitting the DemandedBits/Elts accordingly.

The AMDGPU backend needed an extra  (srl (and x, c1 << c2), c2) -> (and (srl(x, c2), c1) combine to encourage BFE creation, I investigated putting this in DAGComb
but it caused a lot of noise on other targets - some improvements, some regressions.

The X86 changes are all definite wins.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360552 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/TargetLowering.cpp
lib/Target/X86/X86RegisterInfo.cpp
lib/Target/X86/X86RegisterInfo.h
test/CodeGen/X86/bitcast-setcc-256.ll
test/CodeGen/X86/bitcast-setcc-512.ll
test/CodeGen/X86/bitcast-vector-bool.ll
test/CodeGen/X86/dagcombine-cse.ll
test/CodeGen/X86/movmsk-cmp.ll
test/CodeGen/X86/pr41619.ll [new file with mode: 0644]