[AArch64] Improve codegen for inverted overflow checking intrinsics

[AArch64] Improve codegen for inverted overflow checking intrinsics

E.g. if we have a (xor(overflow-bit), 1) where overflow-bit comes from an
intrinsic like llvm.sadd.with.overflow then we can kill the xor and use the
inverted condition code for the CSEL.

rdar://28495949

Reviewed By: kristof.beyls

Differential Revision: https://reviews.llvm.org/D38160

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315205 91177308-0d34-0410-b5e6-96231b3b80d8