]> granicus.if.org Git - llvm/commit
projects / llvm / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 2d4a728) | patch
AMDGPU: Don't rely on m0 being -1 for GWS offsets
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 19 Jul 2019 20:01:24 +0000 (20:01 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 19 Jul 2019 20:01:24 +0000 (20:01 +0000)
commitf4452af4fe09a12ed26545e0450e5486b18e9453
tree8e692a07163d73523faaf749b9e185221f2ed5f8tree | snapshot
parent2d4a72809cd3229a5b4f8a56e905f865e3b95fb1commit | diff
AMDGPU: Don't rely on m0 being -1 for GWS offsets

This only works if the high bits of m0 are also 0, so m0 would have to
be set to 0xffff.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366608 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp diff | blob | history
test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.barrier.ll diff | blob | history
test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.init.ll diff | blob | history
test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.br.ll diff | blob | history
test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.p.ll diff | blob | history
test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.release.all.ll diff | blob | history
test/CodeGen/AMDGPU/llvm.amdgcn.ds.gws.sema.v.ll diff | blob | history
Unnamed repository; edit this file 'description' to name the repository.