]> granicus.if.org Git - llvm/commit
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).
authorKristof Beyls <kristof.beyls@arm.com>
Wed, 28 Jun 2017 07:07:03 +0000 (07:07 +0000)
committerKristof Beyls <kristof.beyls@arm.com>
Wed, 28 Jun 2017 07:07:03 +0000 (07:07 +0000)
commitf41c3c9239734af0a6c543430ea4ffd2dfe736cb
tree6d9b1a7c9a0d1534eba5b16c62767766b85fcb86
parent61e059d1711dccc3dfedf005471a653743f13c34
[ARM] Make -mcpu=generic schedule for an in-order core (Cortex-A8).

The benchmarking summarized in
http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed
this is beneficial for a wide range of cores.

As is to be expected, quite a few small adaptations are needed to the
regressions tests, as the difference in scheduling results in:
- Quite a few small instruction schedule differences.
- A few changes in register allocation decisions caused by different
 instruction schedules.
- A few changes in IfConversion decisions, due to a difference in
 instruction schedule and/or the estimated cost of a branch mispredict.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@306514 91177308-0d34-0410-b5e6-96231b3b80d8
48 files changed:
lib/Target/ARM/ARM.td
test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll
test/CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
test/CodeGen/ARM/Windows/tls.ll
test/CodeGen/ARM/arg-copy-elide.ll
test/CodeGen/ARM/arm-and-tst-peephole.ll
test/CodeGen/ARM/arm-position-independence-jump-table.ll
test/CodeGen/ARM/arm-shrink-wrapping-linux.ll
test/CodeGen/ARM/atomic-cmpxchg.ll
test/CodeGen/ARM/bool-ext-inc.ll
test/CodeGen/ARM/cmpxchg-weak.ll
test/CodeGen/ARM/code-placement.ll
test/CodeGen/ARM/cortex-a57-misched-basic.ll
test/CodeGen/ARM/cortexr52-misched-basic.ll
test/CodeGen/ARM/cttz.ll
test/CodeGen/ARM/cttz_vector.ll
test/CodeGen/ARM/cxx-tlscc.ll
test/CodeGen/ARM/fp16-promote.ll
test/CodeGen/ARM/fp16-v3.ll
test/CodeGen/ARM/ifcvt7.ll
test/CodeGen/ARM/illegal-bitfield-loadstore.ll
test/CodeGen/ARM/indirectbr.ll
test/CodeGen/ARM/jump-table-islands.ll
test/CodeGen/ARM/jump-table-tbh.ll
test/CodeGen/ARM/ldm-stm-i256.ll
test/CodeGen/ARM/legalize-unaligned-load.ll
test/CodeGen/ARM/long_shift.ll
test/CodeGen/ARM/misched-fusion-aes.ll
test/CodeGen/ARM/select_const.ll
test/CodeGen/ARM/shift-i64.ll
test/CodeGen/ARM/swifterror.ll
test/CodeGen/ARM/vcgt.ll
test/CodeGen/ARM/vector-DAGCombine.ll
test/CodeGen/ARM/vext.ll
test/CodeGen/ARM/vfp.ll
test/CodeGen/ARM/vld1.ll
test/CodeGen/ARM/vld2.ll
test/CodeGen/ARM/vld3.ll
test/CodeGen/ARM/vld4.ll
test/CodeGen/ARM/vlddup.ll
test/CodeGen/ARM/vldlane.ll
test/CodeGen/ARM/vpadd.ll
test/CodeGen/ARM/vst1.ll
test/CodeGen/ARM/vst4.ll
test/CodeGen/ARM/vstlane.ll
test/CodeGen/ARM/vuzp.ll
test/CodeGen/Thumb2/constant-islands-new-island.ll
test/CodeGen/Thumb2/thumb2-ifcvt2.ll