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author | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Mon, 1 Jul 2019 17:04:57 +0000 (17:04 +0000) | ||
committer | Matt Arsenault <Matthew.Arsenault@amd.com> | |
Mon, 1 Jul 2019 17:04:57 +0000 (17:04 +0000) | ||
commit | f3b2d689fe32c5082d48d74d309656891fcfda62 | |
tree | 776d6c7b53874a07cf9f5133985d3bfa45e87272 | tree | snapshot |
parent | 914425994ea7a896ac980a11f24f741dfd48e45b | commit | diff |
include/llvm/IR/IntrinsicsAMDGPU.td | diff | blob | history | |
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | diff | blob | history | |
test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir | [new file with mode: 0644] | blob |
test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir | [new file with mode: 0644] | blob |