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(parent: f61ca1e) | patch
Now that we have more cpu feature bits, properly document SSE4a as such.
authorPeter Johnson <peter@tortall.net>
Wed, 12 Sep 2007 07:10:26 +0000 (07:10 -0000)
committerPeter Johnson <peter@tortall.net>
Wed, 12 Sep 2007 07:10:26 +0000 (07:10 -0000)
commitf0e2e9a262fef648031da856e57254272613e460
tree21fc0a601281e173402b9c4fbc2b900e83398a8atree | snapshot
parentf61ca1e37934ec87478520fb3c586028408e670acommit | diff
Now that we have more cpu feature bits, properly document SSE4a as such.
Also correct name of k8 chip (clawhammer) and add venice, k10 processors.

svn path=/trunk/yasm/; revision=1946
modules/arch/x86/gen_x86_insn.py diff | blob | history
modules/arch/x86/x86arch.h diff | blob | history
modules/arch/x86/x86cpu.gperf diff | blob | history
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