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AMDGPU: Correct DS implementation of areLoadsFromSameBasePtr
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 8 Mar 2019 20:30:50 +0000 (20:30 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 8 Mar 2019 20:30:50 +0000 (20:30 +0000)
commitf031b0c0443e85b59ec926fed6b8a1027b65d13d
tree47ef1fe1763888ec092937eb0cf75e3ab5a6a936tree | snapshot
parentc30eca2a728d6c9b1ac09833dc8e0e8f0039c536commit | diff
AMDGPU: Correct DS implementation of areLoadsFromSameBasePtr

This was checking the wrong operands for the base register and the
offsets. The indexes are shifted by the number of output registers
from the machine instruction definition, and the chain is moved to the
end.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355722 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/SIInstrInfo.cpp diff | blob | history
test/CodeGen/AMDGPU/ds-combine-with-dependence.ll diff | blob | history
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