Re-commit r355104: "[AArch64][GlobalISel] Add support for 64 bit vector shuffle using...

Re-commit r355104: "[AArch64][GlobalISel] Add support for 64 bit vector shuffle using TBL1."

The code to materialize a mask from a constant pool load tried to use a 128 bit
LDR to load a 64 bit constant pool entry, which was 8 byte aligned. This resulted
in a link failure in the NEON tests in the test suite since the LDR address was
unaligned. This change fixes that to instead emit a 64 bit LDR if the entry is
64 bit, before converting back to a 128 bit register for the TBL.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355326 91177308-0d34-0410-b5e6-96231b3b80d8