]> granicus.if.org Git - llvm/commit
[x86] use more phadd for reductions
authorSanjay Patel <spatel@rotateright.com>
Tue, 16 Jul 2019 21:30:41 +0000 (21:30 +0000)
committerSanjay Patel <spatel@rotateright.com>
Tue, 16 Jul 2019 21:30:41 +0000 (21:30 +0000)
commiteea9c78cfda6434005ab02b43de14fc650271619
treef96711716617ff51efa0e0540c4c24ad7d1ec641
parent1374e00f70c1fa8a0b8cda16ba7bd0719d867671
[x86] use more phadd for reductions

This is part of what is requested by PR42023:
https://bugs.llvm.org/show_bug.cgi?id=42023

There's an extension needed for FP add, but exactly how we would specify
that using flags is not clear to me, so I left that as a TODO.
We're still missing patterns for partial reductions when the input vector
is 256-bit or 512-bit, but I think that's a failure of vector narrowing.
If we can reduce the widths, then this matching should work on those tests.

Differential Revision: https://reviews.llvm.org/D64760

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366268 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/phaddsub-extract.ll
test/CodeGen/X86/vector-reduce-add-widen.ll
test/CodeGen/X86/vector-reduce-add.ll