]> granicus.if.org Git - llvm/commit
[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX
authorBjorn Pettersson <bjorn.a.pettersson@ericsson.com>
Tue, 3 Sep 2019 19:35:07 +0000 (19:35 +0000)
committerBjorn Pettersson <bjorn.a.pettersson@ericsson.com>
Tue, 3 Sep 2019 19:35:07 +0000 (19:35 +0000)
commitec070e1a4527abe7a7b561def097c7e2317fdc72
treeae84573e558e7b8e86ab4d6599355adcbdc257d2
parentb1f841b1ce3d774f0085912af25b8cfb62854820
[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX

Summary:
Simplify the right shift of the intermediate result (given
in four parts) by using funnel shift.

There are some impact on lit tests, but that seems to be
related to register allocation differences due to how FSHR
is expanded on X86 (giving a slightly different operand order
for the OR operations compared to the old code).

Reviewers: leonardchan, RKSimon, spatel, lebedev.ri

Reviewed By: RKSimon

Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, s.egerton, pzheng, bevinh, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67036

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370813 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
test/CodeGen/RISCV/addcarry.ll
test/CodeGen/X86/smul_fix.ll
test/CodeGen/X86/smul_fix_sat.ll
test/CodeGen/X86/umul_fix.ll