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(parent: 232c3d5) | patch
[AArch64] Enable FeatureFuseAES on Cortex-A72.
authorFlorian Hahn <florian.hahn@arm.com>
Mon, 15 May 2017 15:15:22 +0000 (15:15 +0000)
committerFlorian Hahn <florian.hahn@arm.com>
Mon, 15 May 2017 15:15:22 +0000 (15:15 +0000)
commiteb48e7d58f8d20f22bd7babfd04b41e6855f94af
tree01b58c4514621c2b500aa72eaea5905f33aad900tree | snapshot
parent232c3d52eaffc97a0ef7db8fcb9a9a087429d0dccommit | diff
[AArch64] Enable FeatureFuseAES on Cortex-A72.

This patch enables fusing dependent AESE/AESMC and AESD/AESIMC
instruction pairs on Cortex-A72, as recommended in the Software
Optimization Guide, section 4.10.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@303073 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64.td diff | blob | history
test/CodeGen/AArch64/misched-fusion-aes.ll diff | blob | history
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