[AArch64][GlobalISel] Implement partial support for G_SHUFFLE_VECTOR

[AArch64][GlobalISel] Implement partial support for G_SHUFFLE_VECTOR

This change makes some basic type combinations for G_SHUFFLE_VECTOR legal, and
implements them with a very pessimistic TBL2 instruction in the selector.

For TBL2, support is also needed to generate constant pool entries and load from
them in order to materialize the mask register.

Currently supports <2 x s64> and <4 x s32> result types.

Differential Revision: https://reviews.llvm.org/D58466

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354521 91177308-0d34-0410-b5e6-96231b3b80d8