]> granicus.if.org Git - llvm/commit
[MIPS GlobalISel] Select branch instructions
authorPetar Avramovic <Petar.Avramovic@rt-rk.com>
Thu, 14 Feb 2019 11:39:53 +0000 (11:39 +0000)
committerPetar Avramovic <Petar.Avramovic@rt-rk.com>
Thu, 14 Feb 2019 11:39:53 +0000 (11:39 +0000)
commite817e7373adc3eba41700a56418adcdbfeafe838
tree604de60c42e08e1fec18b4d133fc038eb3279ab3
parentd9bd97c13210f6d20edf4e95048af133ddb327ae
[MIPS GlobalISel] Select branch instructions

Select G_BR and G_BRCOND for MIPS32.
Unconditional branch G_BR does not have register operand,
for that reason we only add tests.
Since conditional branch G_BRCOND compares register to zero on MIPS32,
explicit extension must be performed on i1 condition in order to set
high bits to appropriate value.

Differential Revision: https://reviews.llvm.org/D58182

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@354022 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
lib/Target/Mips/MipsInstructionSelector.cpp
lib/Target/Mips/MipsLegalizerInfo.cpp
lib/Target/Mips/MipsRegisterBankInfo.cpp
test/CodeGen/Mips/GlobalISel/instruction-select/branch.mir [new file with mode: 0644]
test/CodeGen/Mips/GlobalISel/legalizer/branch.mir [new file with mode: 0644]
test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll [new file with mode: 0644]
test/CodeGen/Mips/GlobalISel/regbankselect/branch.mir [new file with mode: 0644]