]> granicus.if.org Git - llvm/commit
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.
authorCraig Topper <craig.topper@intel.com>
Fri, 30 Aug 2019 17:35:08 +0000 (17:35 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 30 Aug 2019 17:35:08 +0000 (17:35 +0000)
commite71312fb28dc7e0cff6b0670e67d0141a73f26ed
tree76b384d0c307c2f89679e40a78f8cdd22cb1eb04
parent7adbcdcc55c2d331eb90119c26d80e287895a59f
[X86] Pass v32i16/v64i8 in zmm registers on KNL target.

gcc and icc pass these types in zmm registers in zmm registers.

This patch implements a quick hack to override the register
type before calling convention handling to one that is legal.
Longer term we might want to do something similar to 256-bit
integer registers on AVX1 where we just split all the operations.

Fixes PR42957

Differential Revision: https://reviews.llvm.org/D66708

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370495 91177308-0d34-0410-b5e6-96231b3b80d8
69 files changed:
docs/ReleaseNotes.rst
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/all-ones-vector.ll
test/CodeGen/X86/avg-mask.ll
test/CodeGen/X86/avg.ll
test/CodeGen/X86/avx512-calling-conv.ll
test/CodeGen/X86/avx512-ext.ll
test/CodeGen/X86/avx512-insert-extract.ll
test/CodeGen/X86/avx512-logic.ll
test/CodeGen/X86/avx512-mask-op.ll
test/CodeGen/X86/avx512-select.ll
test/CodeGen/X86/avx512-trunc.ll
test/CodeGen/X86/avx512-vbroadcast.ll
test/CodeGen/X86/avx512-vbroadcasti128.ll
test/CodeGen/X86/avx512-vbroadcasti256.ll
test/CodeGen/X86/bitcast-and-setcc-512.ll
test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
test/CodeGen/X86/bitcast-setcc-512.ll
test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
test/CodeGen/X86/build-vector-512.ll
test/CodeGen/X86/combine-sdiv.ll
test/CodeGen/X86/fast-isel-nontemporal.ll
test/CodeGen/X86/fast-isel-vecload.ll
test/CodeGen/X86/kshift.ll
test/CodeGen/X86/madd.ll
test/CodeGen/X86/masked_store_trunc.ll
test/CodeGen/X86/masked_store_trunc_ssat.ll
test/CodeGen/X86/masked_store_trunc_usat.ll
test/CodeGen/X86/merge-consecutive-loads-512.ll
test/CodeGen/X86/midpoint-int-vec-512.ll
test/CodeGen/X86/movmsk-cmp.ll
test/CodeGen/X86/nontemporal-loads-2.ll
test/CodeGen/X86/nontemporal-loads.ll
test/CodeGen/X86/pmul.ll
test/CodeGen/X86/pmulh.ll
test/CodeGen/X86/shuffle-vs-trunc-512.ll
test/CodeGen/X86/subvector-broadcast.ll
test/CodeGen/X86/var-permute-512.ll
test/CodeGen/X86/vec_shift6.ll
test/CodeGen/X86/vector-bitreverse.ll
test/CodeGen/X86/vector-compare-results.ll
test/CodeGen/X86/vector-fshl-512.ll
test/CodeGen/X86/vector-fshl-rot-512.ll
test/CodeGen/X86/vector-fshr-512.ll
test/CodeGen/X86/vector-fshr-rot-512.ll
test/CodeGen/X86/vector-idiv-sdiv-512.ll
test/CodeGen/X86/vector-idiv-udiv-512.ll
test/CodeGen/X86/vector-lzcnt-512.ll
test/CodeGen/X86/vector-popcnt-512.ll
test/CodeGen/X86/vector-reduce-and-bool.ll
test/CodeGen/X86/vector-reduce-mul.ll
test/CodeGen/X86/vector-reduce-or-bool.ll
test/CodeGen/X86/vector-reduce-xor-bool.ll
test/CodeGen/X86/vector-rotate-512.ll
test/CodeGen/X86/vector-sext.ll
test/CodeGen/X86/vector-shift-ashr-512.ll
test/CodeGen/X86/vector-shift-lshr-512.ll
test/CodeGen/X86/vector-shift-shl-512.ll
test/CodeGen/X86/vector-shuffle-512-v32.ll
test/CodeGen/X86/vector-shuffle-512-v64.ll
test/CodeGen/X86/vector-shuffle-avx512.ll
test/CodeGen/X86/vector-shuffle-v1.ll
test/CodeGen/X86/vector-trunc-packus.ll
test/CodeGen/X86/vector-trunc-ssat.ll
test/CodeGen/X86/vector-trunc-usat.ll
test/CodeGen/X86/vector-trunc.ll
test/CodeGen/X86/vector-tzcnt-512.ll
test/CodeGen/X86/vector-zext.ll
test/CodeGen/X86/viabs.ll