[mips] Fix lowering load/store instruction in PIC case

[mips] Fix lowering load/store instruction in PIC case

If an operand of the `lw/sw` instructions is a symbol, these instructions
incorrectly lowered using not-position-independent chain of commands.
For PIC code we should use `lw/addiu` instructions with the `R_MIPS_GOT16`
and `R_MIPS_LO16` relocations respectively. Instead of that LLVM generates
position dependent code with the `R_MIPS_HI16` and `R_MIPS_LO16`
relocations.

This patch provides a fix for the bug by handling PIC case separately in
the `MipsAsmParser::expandMemInst`. The main idea is to generate a chain
of PIC instructions to load a symbol address into a register and then
load the address content.

The fix is not optimal and does not fix all PIC-related problems. This
is a task for subsequent patches.

Differential Revision: https://reviews.llvm.org/D65524

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@367580 91177308-0d34-0410-b5e6-96231b3b80d8