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(parent: 08f4489) | patch
[X86] Add a DAG combine for turning *_extend_vector_inreg+load into an appropriate...
authorCraig Topper <craig.topper@intel.com>
Tue, 2 Jul 2019 23:20:03 +0000 (23:20 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 2 Jul 2019 23:20:03 +0000 (23:20 +0000)
commite2754882f63d7dad2bcd1be72261c7342143f646
tree97dc2894d1e107b203a4f8fd56ca072910b3ff54tree | snapshot
parent08f448967a7db1b3ec7efd7f1b0693ffc23ae916commit | diff
[X86] Add a DAG combine for turning *_extend_vector_inreg+load into an appropriate extload if the load isn't volatile.

Remove the corresponding isel patterns that did the same thing without checking for volatile.

This fixes another variation of PR42079

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364977 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp diff | blob | history
lib/Target/X86/X86InstrAVX512.td diff | blob | history
lib/Target/X86/X86InstrSSE.td diff | blob | history
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