]> granicus.if.org Git - llvm/commit
[InstSimplify] vector div/rem with any zero element in divisor is undef
authorSanjay Patel <spatel@rotateright.com>
Thu, 9 Mar 2017 16:20:52 +0000 (16:20 +0000)
committerSanjay Patel <spatel@rotateright.com>
Thu, 9 Mar 2017 16:20:52 +0000 (16:20 +0000)
commitdccf5a132022d8f0c360c50415b2c97fc217415e
treefa6ff0db91ff89dd4e24ef39b7a015f286a8bc1a
parentf04eaba5c780e37c73998e6d2708a80c57309890
[InstSimplify] vector div/rem with any zero element in divisor is undef

This was suggested as a DAG simplification in the review for rL297026 :
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20170306/435253.html
...but let's start with IR since we have actual docs for IR (LangRef).

Differential Revision:
https://reviews.llvm.org/D30665

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297390 91177308-0d34-0410-b5e6-96231b3b80d8
docs/LangRef.rst
lib/Analysis/InstructionSimplify.cpp
test/Transforms/InstCombine/vector-urem.ll
test/Transforms/InstSimplify/div.ll
test/Transforms/InstSimplify/rem.ll