granicus.if.org Git - llvm/commit

]> granicus.if.org Git - llvm/commit

author	Nirav Dave <niravd@google.com>
	Thu, 26 Jan 2017 16:46:13 +0000 (16:46 +0000)
committer	Nirav Dave <niravd@google.com>
	Thu, 26 Jan 2017 16:46:13 +0000 (16:46 +0000)
commit	d9031ef908317e4f2303ea474efb53441aff2c29
tree	275bd44d7abfb3ae4b4050d04a32fc948c239972	tree \| snapshot
parent	eab2fdc64a99682a4422b894755496437412e70c	commit \| diff

Revert "In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled."

This reverts commit r293184 which is failing in LTO builds

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293188 91177308-0d34-0410-b5e6-96231b3b80d8

71 files changed:

include/llvm/Target/TargetLowering.h		diff \| blob \| history
lib/CodeGen/SelectionDAG/DAGCombiner.cpp		diff \| blob \| history
lib/CodeGen/TargetLoweringBase.cpp		diff \| blob \| history
lib/Target/AArch64/AArch64ISelLowering.cpp		diff \| blob \| history
lib/Target/AMDGPU/AMDGPUISelLowering.cpp		diff \| blob \| history
lib/Target/ARM/ARMISelLowering.h		diff \| blob \| history
test/CodeGen/AArch64/argument-blocks.ll		diff \| blob \| history
test/CodeGen/AArch64/arm64-abi.ll		diff \| blob \| history
test/CodeGen/AArch64/arm64-memset-inline.ll		diff \| blob \| history
test/CodeGen/AArch64/arm64-variadic-aapcs.ll		diff \| blob \| history
test/CodeGen/AArch64/merge-store.ll		diff \| blob \| history
test/CodeGen/AArch64/vector_merge_dep_check.ll		diff \| blob \| history
test/CodeGen/AMDGPU/debugger-insert-nops.ll		diff \| blob \| history
test/CodeGen/AMDGPU/insert_vector_elt.ll		diff \| blob \| history
test/CodeGen/AMDGPU/merge-stores.ll		diff \| blob \| history
test/CodeGen/AMDGPU/private-element-size.ll		diff \| blob \| history
test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll		diff \| blob \| history
test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll		diff \| blob \| history
test/CodeGen/ARM/alloc-no-stack-realign.ll		diff \| blob \| history
test/CodeGen/ARM/gpr-paired-spill.ll		diff \| blob \| history
test/CodeGen/ARM/ifcvt10.ll		diff \| blob \| history
test/CodeGen/ARM/static-addr-hoisting.ll		diff \| blob \| history
test/CodeGen/BPF/undef.ll		diff \| blob \| history
test/CodeGen/MSP430/Inst16mm.ll		diff \| blob \| history
test/CodeGen/Mips/cconv/arguments-float.ll		diff \| blob \| history
test/CodeGen/Mips/cconv/arguments-varargs.ll		diff \| blob \| history
test/CodeGen/Mips/fastcc.ll		diff \| blob \| history
test/CodeGen/Mips/load-store-left-right.ll		diff \| blob \| history
test/CodeGen/Mips/micromips-li.ll		diff \| blob \| history
test/CodeGen/Mips/mips64-f128.ll		diff \| blob \| history
test/CodeGen/Mips/mno-ldc1-sdc1.ll		diff \| blob \| history
test/CodeGen/Mips/msa/f16-llvm-ir.ll		diff \| blob \| history
test/CodeGen/Mips/msa/i5_ld_st.ll		diff \| blob \| history
test/CodeGen/Mips/o32_cc_byval.ll		diff \| blob \| history
test/CodeGen/Mips/o32_cc_vararg.ll		diff \| blob \| history
test/CodeGen/PowerPC/anon_aggr.ll		diff \| blob \| history
test/CodeGen/PowerPC/complex-return.ll		diff \| blob \| history
test/CodeGen/PowerPC/jaggedstructs.ll		diff \| blob \| history
test/CodeGen/PowerPC/ppc64-align-long-double.ll		diff \| blob \| history
test/CodeGen/PowerPC/structsinmem.ll		diff \| blob \| history
test/CodeGen/PowerPC/structsinregs.ll		diff \| blob \| history
test/CodeGen/SystemZ/unaligned-01.ll		diff \| blob \| history
test/CodeGen/Thumb/2010-07-15-debugOrdering.ll		diff \| blob \| history
test/CodeGen/Thumb/stack-access.ll		diff \| blob \| history
test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll		diff \| blob \| history
test/CodeGen/X86/2012-11-28-merge-store-alias.ll		diff \| blob \| history
test/CodeGen/X86/MergeConsecutiveStores.ll		diff \| blob \| history
test/CodeGen/X86/avx512-mask-op.ll		diff \| blob \| history
test/CodeGen/X86/chain_order.ll		diff \| blob \| history
test/CodeGen/X86/clear_upper_vector_element_bits.ll		diff \| blob \| history
test/CodeGen/X86/combiner-aa-0.ll	[new file with mode: 0644]	blob
test/CodeGen/X86/combiner-aa-1.ll	[new file with mode: 0644]	blob
test/CodeGen/X86/copy-eflags.ll		diff \| blob \| history
test/CodeGen/X86/dag-merge-fast-accesses.ll		diff \| blob \| history
test/CodeGen/X86/dont-trunc-store-double-to-float.ll		diff \| blob \| history
test/CodeGen/X86/extractelement-legalization-store-ordering.ll		diff \| blob \| history
test/CodeGen/X86/i256-add.ll		diff \| blob \| history
test/CodeGen/X86/i386-shrink-wrapping.ll		diff \| blob \| history
test/CodeGen/X86/live-range-nosubreg.ll		diff \| blob \| history
test/CodeGen/X86/merge-consecutive-loads-128.ll		diff \| blob \| history
test/CodeGen/X86/merge-consecutive-loads-256.ll		diff \| blob \| history
test/CodeGen/X86/merge-store-partially-alias-loads.ll		diff \| blob \| history
test/CodeGen/X86/pr18023.ll	[new file with mode: 0644]	blob
test/CodeGen/X86/split-store.ll		diff \| blob \| history
test/CodeGen/X86/stores-merging.ll		diff \| blob \| history
test/CodeGen/X86/vector-compare-results.ll		diff \| blob \| history
test/CodeGen/X86/vector-shuffle-variable-128.ll		diff \| blob \| history
test/CodeGen/X86/vector-shuffle-variable-256.ll		diff \| blob \| history
test/CodeGen/X86/vectorcall.ll		diff \| blob \| history
test/CodeGen/X86/win32-eh.ll		diff \| blob \| history
test/CodeGen/XCore/varargs.ll		diff \| blob \| history

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