]> granicus.if.org Git - llvm/commit
[X86][AVX512] Improve lowering of AVX512 test intrinsics
authorUriel Korach <uriel.korach@intel.com>
Mon, 6 Nov 2017 09:22:38 +0000 (09:22 +0000)
committerUriel Korach <uriel.korach@intel.com>
Mon, 6 Nov 2017 09:22:38 +0000 (09:22 +0000)
commitd8ea26422cf6ead591815847a79f6d418baf2d00
tree2647234d1f0b35ec37d11f3ad56dda1a986d801a
parent16b230fc73d69b6cf921f6506dca7c7f06bf7fa9
[X86][AVX512] Improve lowering of AVX512 test intrinsics

Added TESTM and TESTNM to the list of instructions that already zeroing unused upper bits
and does not need the redundant shift left and shift right instructions afterwards.
Added a pattern for TESTM and TESTNM in iselLowering, so now icmp(neq,and(X,Y), 0) goes folds into TESTM
and icmp(eq,and(X,Y), 0) goes folds into TESTNM
This commit is a preparation for lowering the test and testn X86 intrinsics to IR.

Differential Revision: https://reviews.llvm.org/D38732

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317465 91177308-0d34-0410-b5e6-96231b3b80d8
12 files changed:
lib/Target/X86/X86ISelDAGToDAG.cpp
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/avx512-skx-insert-subvec.ll
test/CodeGen/X86/avx512bw-vec-test-testn.ll
test/CodeGen/X86/avx512bwvl-vec-test-testn.ll
test/CodeGen/X86/avx512f-vec-test-testn.ll
test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
test/CodeGen/X86/avx512vl-vec-test-testn.ll
test/CodeGen/X86/compress_expand.ll
test/CodeGen/X86/masked_gather_scatter.ll
test/CodeGen/X86/masked_memop.ll
test/CodeGen/X86/setcc-lowering.ll