]> granicus.if.org Git - llvm/commit
[X86] Merge the different CMOV instructions for each condition code into single instr...
authorCraig Topper <craig.topper@intel.com>
Fri, 5 Apr 2019 19:27:41 +0000 (19:27 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 5 Apr 2019 19:27:41 +0000 (19:27 +0000)
commitd8490747ade4067a4bcfcf45ee95d8265c975394
treebb1efc7569f6957732c3395750adae51267b5d9d
parent4fb52f8a323de1adffb44a5c535d5b3726c71a5f
[X86] Merge the different CMOV instructions for each condition code into single instructions that store the condition code as an immediate.

Summary:
Reorder the condition code enum to match their encodings. Move it to MC layer so it can be used by the scheduler models.

This avoids needing an isel pattern for each condition code. And it removes
translation switches for converting between CMOV instructions and condition
codes.

Now the printer, encoder and disassembler take care of converting the immediate.
We use InstAliases to handle the assembly matching. But we print using the
asm string in the instruction definition. The instruction itself is marked
IsCodeGenOnly=1 to hide it from the assembly parser.

This does complicate the scheduler models a little since we can't assign the
A and BE instructions to a separate class now.

I plan to make similar changes for SETcc and Jcc.

Reviewers: RKSimon, spatel, lebedev.ri, andreadb, courbet

Reviewed By: RKSimon

Subscribers: gchatelet, hiraditya, kristina, lebedev.ri, jdoerfert, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60041

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357800 91177308-0d34-0410-b5e6-96231b3b80d8
40 files changed:
include/llvm/Support/X86DisassemblerDecoderCommon.h
lib/Target/X86/Disassembler/X86Disassembler.cpp
lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
lib/Target/X86/InstPrinter/X86InstPrinterCommon.cpp
lib/Target/X86/InstPrinter/X86InstPrinterCommon.h
lib/Target/X86/MCTargetDesc/X86BaseInfo.h
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
lib/Target/X86/X86CmovConversion.cpp
lib/Target/X86/X86FastISel.cpp
lib/Target/X86/X86FlagsCopyLowering.cpp
lib/Target/X86/X86FrameLowering.cpp
lib/Target/X86/X86ISelDAGToDAG.cpp
lib/Target/X86/X86InstrCMovSetCC.td
lib/Target/X86/X86InstrCompiler.td
lib/Target/X86/X86InstrFoldTables.cpp
lib/Target/X86/X86InstrFormats.td
lib/Target/X86/X86InstrInfo.cpp
lib/Target/X86/X86InstrInfo.h
lib/Target/X86/X86InstrInfo.td
lib/Target/X86/X86SchedBroadwell.td
lib/Target/X86/X86SchedHaswell.td
lib/Target/X86/X86SchedPredicates.td
lib/Target/X86/X86SchedSandyBridge.td
lib/Target/X86/X86SchedSkylakeClient.td
lib/Target/X86/X86SchedSkylakeServer.td
lib/Target/X86/X86Schedule.td
lib/Target/X86/X86ScheduleAtom.td
lib/Target/X86/X86ScheduleBdVer2.td
lib/Target/X86/X86ScheduleBtVer2.td
lib/Target/X86/X86ScheduleSLM.td
lib/Target/X86/X86ScheduleZnver1.td
lib/Target/X86/X86SpeculativeLoadHardening.cpp
test/CodeGen/X86/flags-copy-lowering.mir
test/CodeGen/X86/non-value-mem-operand.mir
test/CodeGen/X86/post-ra-sched-with-debug.mir
test/CodeGen/X86/tail-call-conditional.mir
tools/llvm-exegesis/lib/X86/Target.cpp
unittests/tools/llvm-exegesis/X86/SnippetGeneratorTest.cpp
utils/TableGen/X86RecognizableInstr.cpp
utils/TableGen/X86RecognizableInstr.h