]> granicus.if.org Git - llvm/commit
AMDGPU: Add definitions for scalar store instructions
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 28 Oct 2016 21:55:15 +0000 (21:55 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Fri, 28 Oct 2016 21:55:15 +0000 (21:55 +0000)
commitd6028cdcc7a27e26554e26ed1806766edb06251e
tree89715589fce87bbb239cf48575cf775316ab6d8e
parentbe4e1c4eb0b895057be9f745f999b9ba1ffb45a3
AMDGPU: Add definitions for scalar store instructions

Also add glc bit to the scalar loads since they exist on VI
and change the caching behavior.

This currently has an assembler bug where the glc bit is incorrectly
accepted on SI/CI which do not have it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@285463 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/AMDGPU.td
lib/Target/AMDGPU/AMDGPUSubtarget.h
lib/Target/AMDGPU/SIDefines.h
lib/Target/AMDGPU/SIInstrFormats.td
lib/Target/AMDGPU/SIInstrInfo.cpp
lib/Target/AMDGPU/SIInstrInfo.h
lib/Target/AMDGPU/SMInstructions.td
test/CodeGen/AMDGPU/coalescer-subreg-join.mir
test/CodeGen/MIR/AMDGPU/target-index-operands.mir
test/MC/AMDGPU/smem.s
test/MC/AMDGPU/smrd-err.s