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[TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG -> ANY/ZERO_EXTEND_VEC...
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 19 Jun 2019 13:58:02 +0000 (13:58 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 19 Jun 2019 13:58:02 +0000 (13:58 +0000)
commitd48da2b6432c4a5616f44ca12170f2cfbfdeafac
tree0f0226ad4d51c6fc355f8328eba0dd26e8d26a2atree | snapshot
parentd020d45e35dbdc70285303878a0acfdb7776552ecommit | diff
[TargetLowering] SimplifyDemandedBits SIGN_EXTEND_VECTOR_INREG -> ANY/ZERO_EXTEND_VECTOR_INREG

Simplify SIGN_EXTEND_VECTOR_INREG if the extended bits are not required/known zero.

Matches what we already do for SIGN_EXTEND.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363802 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/TargetLowering.cpp diff | blob | history
test/CodeGen/X86/pmul.ll diff | blob | history
test/CodeGen/X86/xop-ifma.ll diff | blob | history
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