]> granicus.if.org Git - llvm/commit
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64...
authorCraig Topper <craig.topper@intel.com>
Sat, 25 May 2019 06:17:47 +0000 (06:17 +0000)
committerCraig Topper <craig.topper@intel.com>
Sat, 25 May 2019 06:17:47 +0000 (06:17 +0000)
commitd36f33ec25ab2883afd6fa83c97302eac3d320b3
tree848da66dcfbfe0f7589ab0c2a6930da5784be1ab
parent44048f6af6d039a822485b64350e4cb530be9c6f
[X86FixupLEAs] Turn optIncDec into a generic two address LEA optimizer. Support LEA64_32r properly.

INC/DEC is really a special case of a more generic issue. We should also turn leas into add reg/reg or add reg/imm regardless of the slow lea flags.

This also supports LEA64_32 which has 64 bit input registers and 32 bit output registers. So we need to convert the 64 bit inputs to their 32 bit equivalents to check if they are equal to base reg.

One thing to note, the original code preserved the kill flags by adding operands to the new instruction instead of using addReg. But I think tied operands aren't supposed to have the kill flag set. I dropped the kill flags, but I could probably try to preserve it in the add reg/reg case if we think its important. Not sure which operand its supposed to go on for the LEA64_32r instruction due to the super reg implicit uses. Though I'm also not sure those are needed since they were probably just created by an INSERT_SUBREG from a 32-bit input.

Differential Revision: https://reviews.llvm.org/D61472

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@361691 91177308-0d34-0410-b5e6-96231b3b80d8
31 files changed:
lib/Target/X86/X86FixupLEAs.cpp
test/CodeGen/X86/GlobalISel/add-ext.ll
test/CodeGen/X86/GlobalISel/callingconv.ll
test/CodeGen/X86/GlobalISel/gep.ll
test/CodeGen/X86/GlobalISel/memop-scalar.ll
test/CodeGen/X86/MergeConsecutiveStores.ll
test/CodeGen/X86/atomic-unordered.ll
test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
test/CodeGen/X86/bitreverse.ll
test/CodeGen/X86/bswap_tree2.ll
test/CodeGen/X86/bypass-slow-division-32.ll
test/CodeGen/X86/combine-srem.ll
test/CodeGen/X86/dagcombine-shifts.ll
test/CodeGen/X86/fixup-bw-copy.ll
test/CodeGen/X86/fixup-lea.ll
test/CodeGen/X86/imul.ll
test/CodeGen/X86/leaFixup32.mir
test/CodeGen/X86/leaFixup64.mir
test/CodeGen/X86/mul-constant-i16.ll
test/CodeGen/X86/mul-constant-i32.ll
test/CodeGen/X86/mul-constant-i64.ll
test/CodeGen/X86/mul-constant-i8.ll
test/CodeGen/X86/popcnt.ll
test/CodeGen/X86/ragreedy-hoist-spill.ll
test/CodeGen/X86/reverse_branches.ll
test/CodeGen/X86/rotate-extract.ll
test/CodeGen/X86/sat-add.ll
test/CodeGen/X86/twoaddr-lea.ll
test/CodeGen/X86/vector-bitreverse.ll
test/CodeGen/X86/win_coreclr_chkstk.ll
test/Transforms/LoopStrengthReduce/X86/ivchain-X86.ll