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[TargetLowering] SimplifyDemandedBits - Merge ZERO_EXTEND+ZERO_EXTEND_VECTOR_INREG...
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 18 Jun 2019 18:08:30 +0000 (18:08 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Tue, 18 Jun 2019 18:08:30 +0000 (18:08 +0000)
commitd26889bb0fffb3c2ce5929f3b1d4a99e0b35ba47
treeeef2d6b5b6ec8b1bf3d4c2179170aa588fc99a15tree | snapshot
parent3709f6b81ea8e94f6a6b26d015d9216c9435edcecommit | diff
[TargetLowering] SimplifyDemandedBits - Merge ZERO_EXTEND+ZERO_EXTEND_VECTOR_INREG handling

Other than adding consistent demanded elts handling which was a trivial addition, the other differences in functionality will be added in later patches.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363713 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/TargetLowering.cpp diff | blob | history
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