]> granicus.if.org Git - llvm/commit
[PowerPC][Peephole] Combine extsw and sldi after instruction selection
authorKai Luo <lkail@cn.ibm.com>
Tue, 9 Jul 2019 02:55:08 +0000 (02:55 +0000)
committerKai Luo <lkail@cn.ibm.com>
Tue, 9 Jul 2019 02:55:08 +0000 (02:55 +0000)
commitd2608216bb66c9f8f15bf8d6114e581022f54665
treefc5094f2a345f420bac622558db73b5f29117192
parente576cd1a931033bbb58888b85d3dbbae76199f4e
[PowerPC][Peephole] Combine extsw and sldi after instruction selection

Summary:
`extsw` and `sldi` are supposed to be combined if they are in the same
BB in instruction selection phase. This patch handles the case where
extsw and sldi are not in the same BB.

Differential Revision: https://reviews.llvm.org/D63806

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@365430 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/PowerPC/P9InstrResources.td
lib/Target/PowerPC/PPCInstr64Bit.td
lib/Target/PowerPC/PPCMIPeephole.cpp
test/CodeGen/PowerPC/combine-sext-and-shl-after-isel.ll