]> granicus.if.org Git - llvm/commit
[AArch64][SVE] Asm: error on unexpected SVE vector register type suffix
authorSander de Smalen <sander.desmalen@arm.com>
Wed, 27 Mar 2019 17:23:38 +0000 (17:23 +0000)
committerSander de Smalen <sander.desmalen@arm.com>
Wed, 27 Mar 2019 17:23:38 +0000 (17:23 +0000)
commitd0d95f2d77154c8e9993fc2019c3ffc2d36d182c
tree5c1906c0c60e75ad6293b26dd7c9e9e4e1cb7cd5
parent0755a8d19c51909534cca7b02e1db02421998049
[AArch64][SVE] Asm: error on unexpected SVE vector register type suffix

This patch fixes an assembler bug that allowed SVE vector registers to contain a
type suffix when not expected. The SVE unpredicated movprfx instruction is the
only instruction affected.

The following are examples of what was previously valid:

    movprfx z0.b, z0.b
    movprfx z0.b, z0.s
    movprfx z0, z0.s

These instructions are now erroneous.

Patch by Cullen Rhodes (c-rhodes)

Reviewed By: sdesmalen

Differential Revision: https://reviews.llvm.org/D59636

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357094 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
test/MC/AArch64/SVE/ldr-diagnostics.s
test/MC/AArch64/SVE/movprfx-diagnostics.s
test/MC/AArch64/SVE/str-diagnostics.s