]> granicus.if.org Git - llvm/commit
[InstCombine] Teach SimplifyMultipleUseDemandedBits to handle And/Or/Xor known bits...
authorCraig Topper <craig.topper@gmail.com>
Wed, 12 Apr 2017 19:32:47 +0000 (19:32 +0000)
committerCraig Topper <craig.topper@gmail.com>
Wed, 12 Apr 2017 19:32:47 +0000 (19:32 +0000)
commitd0d13f5774d28cc63ea98d9b434e4a84bca46f06
tree47de92b0870a378cb29f2dbdeb30a9dbdfb1bfb5
parent1db7e25e94b4ee8959cef787eb8da09135433249
[InstCombine] Teach SimplifyMultipleUseDemandedBits to handle And/Or/Xor known bits using the LHS/RHS known bits it already acquired without recursing back into computeKnownBits.

This replicates the known bits and constant creation code from the single use case for these instructions and adds it here. The computeKnownBits and constant creation code for other instructions is now in the default case of the opcode switch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@300094 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp