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(parent: b2d28d4) | patch
GlobalISel: Allow bitcount ops to have different result type
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 31 Jan 2019 02:09:57 +0000 (02:09 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 31 Jan 2019 02:09:57 +0000 (02:09 +0000)
commitd08f66450d9941bd12232b80ad37f8771cb0944c
treec3a546d77bd6657a4a21e6199970812504264b93tree | snapshot
parentb2d28d4c3452549b94ddaad1cfc4da138938997fcommit | diff
GlobalISel: Allow bitcount ops to have different result type

For AMDGPU the result is always 32-bit for 64-bit inputs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@352717 91177308-0d34-0410-b5e6-96231b3b80d8
12 files changed:
include/llvm/CodeGen/GlobalISel/LegalizerHelper.h diff | blob | history
include/llvm/Target/GenericOpcodes.td diff | blob | history
lib/CodeGen/GlobalISel/LegalizerHelper.cpp diff | blob | history
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp diff | blob | history
lib/Target/ARM/ARMLegalizerInfo.cpp diff | blob | history
test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir diff | blob | history
test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir [new file with mode: 0644] blob
test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir [new file with mode: 0644] blob
test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir [new file with mode: 0644] blob
test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir [new file with mode: 0644] blob
test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir [new file with mode: 0644] blob
unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp diff | blob | history
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