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(parent: ecb26c9) | patch
GlobalISel/TableGen: Handle setcc patterns
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 29 Aug 2019 01:13:41 +0000 (01:13 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Thu, 29 Aug 2019 01:13:41 +0000 (01:13 +0000)
commitcef7580a71894b1f708160baed0e53216c223eb4
tree41e808cd6194dfd0c68ab34b2b652a90a189eb9ftree | snapshot
parentecb26c9a2fb9c7cf80a749e6025f5721f520e26acommit | diff
GlobalISel/TableGen: Handle setcc patterns

This is a special case because one node maps to two different G_
instructions, and the operand order is changed.

This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually
selected for now since it has the SALU and VALU complication to deal
with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370280 91177308-0d34-0410-b5e6-96231b3b80d8
15 files changed:
include/llvm/CodeGen/GlobalISel/InstructionSelector.h diff | blob | history
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h diff | blob | history
include/llvm/Target/GlobalISel/SelectionDAGCompat.td diff | blob | history
include/llvm/Target/TargetSelectionDAG.td diff | blob | history
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp diff | blob | history
lib/Target/AMDGPU/AMDGPURegisterBanks.td diff | blob | history
test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir [new file with mode: 0644] blob
test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir [new file with mode: 0644] blob
test/CodeGen/Mips/GlobalISel/instruction-select/mul.mir diff | blob | history
test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll diff | blob | history
test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll diff | blob | history
test/CodeGen/Mips/GlobalISel/llvm-ir/mul.ll diff | blob | history
test/TableGen/Common/GlobalISelEmitterCommon.td diff | blob | history
test/TableGen/GlobalISelEmitter-setcc.td [new file with mode: 0644] blob
utils/TableGen/GlobalISelEmitter.cpp diff | blob | history
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