]> granicus.if.org Git - llvm/commit
[X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all sign bits.
authorCraig Topper <craig.topper@intel.com>
Mon, 1 Jan 2018 04:52:58 +0000 (04:52 +0000)
committerCraig Topper <craig.topper@intel.com>
Mon, 1 Jan 2018 04:52:58 +0000 (04:52 +0000)
commitce169cc70ee72173f20dec76f00b99e31e32f848
tree86cbe837ecba357f2d8e9f68c3a4e2e91e0822e9
parent893d8a79e0f3a80148a1276fbceb7bcdcfa0ead0
[X86] In LowerTruncateVecI1, don't add SHL if the input is known to be all sign bits.

If the input is all sign bits then the LSB through MSB are all the same so we don't need to be move the LSB to the MSB.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321617 91177308-0d34-0410-b5e6-96231b3b80d8
14 files changed:
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/avx512-extract-subvector-load-store.ll
test/CodeGen/X86/avx512-insert-extract.ll
test/CodeGen/X86/avx512-vec-cmp.ll
test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
test/CodeGen/X86/bitcast-and-setcc-128.ll
test/CodeGen/X86/bitcast-and-setcc-256.ll
test/CodeGen/X86/bitcast-setcc-128.ll
test/CodeGen/X86/bitcast-setcc-256.ll
test/CodeGen/X86/bitcast-setcc-512.ll
test/CodeGen/X86/broadcastm-lowering.ll
test/CodeGen/X86/vector-compare-results.ll
test/CodeGen/X86/vector-shuffle-v1.ll
test/CodeGen/X86/x86-interleaved-access.ll