]> granicus.if.org Git - llvm/commit
Merging r368572:
authorHans Wennborg <hans@hanshq.net>
Tue, 13 Aug 2019 12:00:39 +0000 (12:00 +0000)
committerHans Wennborg <hans@hanshq.net>
Tue, 13 Aug 2019 12:00:39 +0000 (12:00 +0000)
commitccc886d363982d2deb7861fc59d5617d707ac126
tree79f93094383a2b1fe29abd8d3a2c0f0b87ac2cc2
parent00237fcc861380c89573f7ccf5caa68e6f1e04bf
Merging r368572:
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r368572 | lenary | 2019-08-12 15:51:00 +0200 (Mon, 12 Aug 2019) | 18 lines

[RISCV] Fix ICE in isDesirableToCommuteWithShift

Summary:
Ana Pazos reported a bug where we were not checking that an APInt would
fit into 64-bits before calling `getSExtValue()`. This caused asserts when
compiling large constants, such as i128s, as happens when compiling compiler-rt.

This patch adds a testcase and makes the callback less error-prone.

Reviewers: apazos, asb, luismarques

Reviewed By: luismarques

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D66081
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_90@368674 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/RISCV/RISCVISelLowering.cpp
test/CodeGen/RISCV/add-before-shl.ll