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[RISCV] Add inline asm constraint A for RISC-V
authorLewis Revill <lewis.revill@embecosm.com>
Fri, 16 Aug 2019 10:23:56 +0000 (10:23 +0000)
committerLewis Revill <lewis.revill@embecosm.com>
Fri, 16 Aug 2019 10:23:56 +0000 (10:23 +0000)
commitc94c0391d99e127e908f2d4a9c8cf8fca0b4c044
treecfe0f565e1e9ce16f91ed61e371f8318bcdf11f8tree | snapshot
parent27cb4e064171b635c6cd9ea16ef3a7d9deacce7ecommit | diff
[RISCV] Add inline asm constraint A for RISC-V

This allows the constraint A to be used in inline asm for RISC-V, which
allows an address held in a register to be used.

This patch adds the minimal amount of code required to get operands with
the right constraints to compile.

Differential Revision: https://reviews.llvm.org/D54295

git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@369093 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Basic/Targets/RISCV.cpp diff | blob | history
test/CodeGen/riscv-inline-asm.c diff | blob | history
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