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[X86] Add VEX_LIG to scalar VEX/EVEX instructions that were missing it.
authorCraig Topper <craig.topper@intel.com>
Tue, 9 Apr 2019 23:30:36 +0000 (23:30 +0000)
committerCraig Topper <craig.topper@intel.com>
Tue, 9 Apr 2019 23:30:36 +0000 (23:30 +0000)
commitc90f68822e5545ce6908de02e645366fefcd763d
treede3741f0dd232e23989783408a3b62f4423fe13etree | snapshot
parent1642cf11e5c1bc91ebeb415277b8890c6d52a224commit | diff
[X86] Add VEX_LIG to scalar VEX/EVEX instructions that were missing it.

Scalar VEX/EVEX instructions don't use the L bit and don't look at it for decoding either.
So we should ignore it in our disassembler.

The missing instructions here were found by grepping the raw tablegen class definitions in
the tablegen debug output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@358040 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86InstrAVX512.td diff | blob | history
lib/Target/X86/X86InstrSSE.td diff | blob | history
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