]> granicus.if.org Git - llvm/commit
[AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics
authorTim Renouf <tpr.llvm@botech.co.uk>
Fri, 22 Mar 2019 14:58:02 +0000 (14:58 +0000)
committerTim Renouf <tpr.llvm@botech.co.uk>
Fri, 22 Mar 2019 14:58:02 +0000 (14:58 +0000)
commitc89bf6fdf363051a396c007712215050b8ad2eef
treededd29c45b62c70e8c0ae4af8561ba2e864cd69b
parent158b5b6e513299337bbf099a0c56245a567c724f
[AMDGPU] Implemented dwordx3 variants of buffer/tbuffer load/store intrinsics

Now we have vec3 MVTs, this commit implements dwordx3 variants of the
buffer intrinsics.

On gfx6, a dwordx3 buffer load intrinsic is implemented as a dwordx4
instruction, and a dwordx3 buffer store intrinsic is not supported.
We need to support the dwordx3 load intrinsic because it is generated by
subtarget-unaware code in InstCombine.

Differential Revision: https://reviews.llvm.org/D58904

Change-Id: I016729d8557b98a52f529638ae97c340a5922a4e

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@356755 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/AMDGPUISelLowering.cpp
lib/Target/AMDGPU/AMDGPUISelLowering.h
lib/Target/AMDGPU/BUFInstructions.td
lib/Target/AMDGPU/SIISelLowering.cpp
lib/Target/AMDGPU/SIISelLowering.h
lib/Target/AMDGPU/SIInstrInfo.td
test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.dwordx3.ll [new file with mode: 0644]
test/CodeGen/AMDGPU/llvm.amdgcn.buffer.store.dwordx3.ll [new file with mode: 0644]
test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.load.dwordx3.ll [new file with mode: 0644]
test/CodeGen/AMDGPU/llvm.amdgcn.tbuffer.store.dwordx3.ll [new file with mode: 0644]
test/MC/AMDGPU/mtbuf.s