]> granicus.if.org Git - llvm/commit
[TableGen][MC] Fix a few places where we didn't hide the underlying type of LaneBitma...
authorCraig Topper <craig.topper@intel.com>
Fri, 14 Jul 2017 18:30:09 +0000 (18:30 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 14 Jul 2017 18:30:09 +0000 (18:30 +0000)
commitc68f8f2fd3c004e60e958761b00a9ae4bce97e2d
tree5910e9fe30f3c17adbdff2538227a58e4dc7df78
parentcb105529db3efec7d2de569f14fb12987f035405
[TableGen][MC] Fix a few places where we didn't hide the underlying type of LaneBitmask very well.

One place compared with 32, which I've replaced with LaneBitmask::BitWidth.

The other places are shifts of a constant 1 by a lane number. But if LaneBitmask were to be a larger type than 32-bits like 64-bits, the 1 would need to be 1ULL to do a 64-bit shift. To hide this I've added a LanebitMask::getLane that hides the shift and make sures the 1 is casted to correct type first.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@308042 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/MC/LaneBitmask.h
utils/TableGen/CodeGenRegisters.cpp