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[SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodes
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 10 Nov 2016 22:41:49 +0000 (22:41 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Thu, 10 Nov 2016 22:41:49 +0000 (22:41 +0000)
commitc5bdc92c0d2add3ae467c63d25965c8571a01381
treed113f2b2b594a15209cc512bdb37baec9d877d31tree | snapshot
parenta145558c9a55489e8b5683fea8f086d80e32ca35commit | diff
[SelectionDAG] Add support for vector demandedelts in ADD/SUB opcodes

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286516 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/SelectionDAG.cpp diff | blob | history
test/CodeGen/X86/known-bits-vector.ll diff | blob | history
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