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MIRParser: Allow regclass specification on operand
authorMatthias Braun <matze@braunis.de>
Wed, 18 Jan 2017 00:59:19 +0000 (00:59 +0000)
committerMatthias Braun <matze@braunis.de>
Wed, 18 Jan 2017 00:59:19 +0000 (00:59 +0000)
commitc1fa0731c3def3cacc8491c12e008eeb605f930f
tree4cb05fb09e235886034f692a5c4a9b51fd40fb1etree | snapshot
parent13bc67e541a37da51c8bf46530c90f58cf720b65commit | diff
MIRParser: Allow regclass specification on operand

You can now define the register class of a virtual register on the
operand itself avoiding the need to use a "registers:" block.

Example: "%0:gr64 = COPY %rax"

Differential Revision: https://reviews.llvm.org/D22398

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@292321 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/MIRParser/MIParser.cpp diff | blob | history
lib/CodeGen/MIRParser/MIParser.h diff | blob | history
lib/CodeGen/MIRParser/MIRParser.cpp diff | blob | history
test/CodeGen/MIR/AArch64/register-operand-bank.mir [new file with mode: 0644] blob
test/CodeGen/MIR/X86/register-operand-class-invalid0.mir [new file with mode: 0644] blob
test/CodeGen/MIR/X86/register-operand-class-invalid1.mir [new file with mode: 0644] blob
test/CodeGen/MIR/X86/register-operand-class.mir [new file with mode: 0644] blob
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