]> granicus.if.org Git - llvm/commit
[X86] Correct the ins operand order for MASKPAIR16STORE to match other store instruct...
authorCraig Topper <craig.topper@intel.com>
Fri, 31 May 2019 05:20:27 +0000 (05:20 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 31 May 2019 05:20:27 +0000 (05:20 +0000)
commitc096c07323e4dbb4003d37aca1caec86ff3c0444
tree55d6bcbb2a390c7af591e7bedf380298f265309a
parentc76a61c205e30a2d3d46a4621ffe176a6186cda1
[X86] Correct the ins operand order for MASKPAIR16STORE to match other store instructions.

This makes the 5 address operands come first. And the data operand comes last.

This matches the operand order the instruction is created with. It's also the
expected order in X86MCInstLower. So everything appeared to work, but the
operands didn't match their declared type.

Fixes a -verify-machineinstrs failure.

Also remove the isel patterns from these instructions since they should only
be used for stack spills and reloads. I'm not even sure what types the patterns
were looking for to match.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362193 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86InstrAVX512.td
test/CodeGen/X86/vp2intersect_multiple_pairs.ll