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(parent: a22eace) | patch
(1) Added special register class containing (for now) %fsr.
authorVikram S. Adve <vadve@cs.uiuc.edu>
Tue, 27 May 2003 00:07:13 +0000 (00:07 +0000)
committerVikram S. Adve <vadve@cs.uiuc.edu>
Tue, 27 May 2003 00:07:13 +0000 (00:07 +0000)
commitbfebd79dd11a04974ea71f79a160c31fc45a91af
tree497cc3d2e1a5e1edaac78f3d9ef3be8947dd8687tree | snapshot
parenta22eace55bb17af2728ca494b6d4557bdad82a09commit | diff
(1) Added special register class containing (for now) %fsr.
    Fixed spilling of %fcc[0-3] which are part of %fsr.

(2) Moved some machine-independent reg-class code to class TargetRegInfo
    from SparcReg{Class,}Info.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6343 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/Target/TargetRegInfo.h diff | blob | history
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