[X86][AVX2] Improve lowerShuffleAsRepeatedMaskAndLanePermute permutation of 64-bit...
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Fri, 15 Jul 2016 09:49:12 +0000 (09:49 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Fri, 15 Jul 2016 09:49:12 +0000 (09:49 +0000)
commitbe745b9c8c166fc3efd69a76155cb0b8df8563e2
tree3e3f5ce7607b78286f15f6c659edd2c26920c4ef
parentd7bfcbac2645383aaf5083b40268ce00b45e16fe
[X86][AVX2] Improve lowerShuffleAsRepeatedMaskAndLanePermute permutation of 64-bit sub-lanes

As discussed on PR28136, lowerShuffleAsRepeatedMaskAndLanePermute was attempting to match repeated masks at the 128-bit level and then permute the resultant lanes at the 128-bit (AVX1) or 64-bit (AVX2) sub-lane level.

This change allows us to create the repeated masks at the sub-lane level (and then concat them together to create a 128-bit repeated mask) and then select which sub-lane to permute. This has no effect on the AVX1 codegen.

Fixes PR28136.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@275543 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
test/CodeGen/X86/avx2-conversions.ll
test/CodeGen/X86/avx2-vector-shifts.ll
test/CodeGen/X86/reduce-trunc-shl.ll
test/CodeGen/X86/vector-compare-results.ll
test/CodeGen/X86/vector-shuffle-256-v16.ll
test/CodeGen/X86/vector-shuffle-256-v32.ll
test/CodeGen/X86/vector-shuffle-256-v8.ll
test/CodeGen/X86/vector-trunc-math.ll
test/CodeGen/X86/vector-trunc.ll