]> granicus.if.org Git - llvm/commit
[X86] Use MOVQ for i64 atomic_stores when SSE2 is enabled
authorCraig Topper <craig.topper@intel.com>
Sat, 27 Apr 2019 03:38:15 +0000 (03:38 +0000)
committerCraig Topper <craig.topper@intel.com>
Sat, 27 Apr 2019 03:38:15 +0000 (03:38 +0000)
commitbb63d993091a23293c2be31865a1dd4e4cbe3e7a
treed0fe06f8e306aa6383a18c00033a410636911a7a
parentdfc7fb5622f6259657a82e58173bb7ec121b0aed
[X86] Use MOVQ for i64 atomic_stores when SSE2 is enabled

Summary: If we have SSE2 we can use a MOVQ to store 64-bits and avoid falling back to a cmpxchg8b loop. If its a seq_cst store we need to insert an mfence after the store.

Reviewers: spatel, RKSimon, reames, jfb, efriedma

Reviewed By: RKSimon

Subscribers: hiraditya, dexonsmith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60546

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@359368 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ISelLowering.cpp
lib/Target/X86/X86ISelLowering.h
lib/Target/X86/X86InstrAVX512.td
lib/Target/X86/X86InstrFragmentsSIMD.td
lib/Target/X86/X86InstrSSE.td
test/CodeGen/X86/atomic-fp.ll
test/CodeGen/X86/atomic-load-store-wide.ll
test/CodeGen/X86/atomic-non-integer.ll
test/CodeGen/X86/atomic6432.ll