]> granicus.if.org Git - llvm/commit
[AArch64][GlobalISel] Select patterns which use shifted register operands
authorJessica Paquette <jpaquette@apple.com>
Tue, 20 Aug 2019 22:18:06 +0000 (22:18 +0000)
committerJessica Paquette <jpaquette@apple.com>
Tue, 20 Aug 2019 22:18:06 +0000 (22:18 +0000)
commitbb5c0f6c915efe40ddf26a7052f3bbe15be65186
tree917a2a8f66c92d6ed7a8d5b904d6aa45abd3a210
parent431ef0cefb067de981ed71b1b9c22cd2b757f3a2
[AArch64][GlobalISel] Select patterns which use shifted register operands

This adds GlobalISel equivalents for the following from AArch64InstrFormats:

- arith_shifted_reg32
- arith_shifted_reg64

And partial support for

- logical_shifted_reg32
- logical_shifted_reg32

The only thing missing for the logical cases is support for rotates. Other than
the missing support, the transformation is identical for the arithmetic shifted
register and the logical shifted register.

Lots of tests here:

- Add select-arith-shifted-reg.mir to show that we correctly select add and
sub instructions which use this pattern.

- Add select-logical-shifted-reg.mir to cover patterns which are not shared
between the arithmetic and logical cases.

- Update addsub-shifted.ll to show that we correctly fold shifts into
adds/subs.

- Update eon.ll to show that we can select the eon instruction by folding xors.

Differential Revision: https://reviews.llvm.org/D66163

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@369460 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AArch64/AArch64InstrFormats.td
lib/Target/AArch64/AArch64InstructionSelector.cpp
test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir [new file with mode: 0644]
test/CodeGen/AArch64/GlobalISel/select-logical-shifted-reg.mir [new file with mode: 0644]
test/CodeGen/AArch64/addsub-shifted.ll
test/CodeGen/AArch64/eon.ll