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AMDGPU: Split wide vectors of i16/f16 into 32-bit regs on calls
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 31 Jul 2018 19:17:47 +0000 (19:17 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 31 Jul 2018 19:17:47 +0000 (19:17 +0000)
commitb9d99ce19e456aaa9353b623568c49ded6c6e418
tree0ea0c6bcc34a0381a02240884c87acaa692bb1bdtree | snapshot
parenta7336f29220616427920dabdd5535a6abebcb3bacommit | diff
AMDGPU: Split wide vectors of i16/f16 into 32-bit regs on calls

This improves code for the same reasons as scalarizing 32-bit
element vectors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338418 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/SIISelLowering.cpp diff | blob | history
test/CodeGen/AMDGPU/call-argument-types.ll diff | blob | history
test/CodeGen/AMDGPU/mad-mix-lo.ll diff | blob | history
test/CodeGen/AMDGPU/mul.i16.ll diff | blob | history
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